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ASM3P622S00EG-16-TT

产品描述Clock Generator, 20MHz, CMOS, PDSO16, 4.40 MM, GREEN, TSSOP-16
产品类别嵌入式处理器和控制器    微控制器和处理器   
文件大小678KB,共15页
制造商PulseCore Semiconductor Corporation
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ASM3P622S00EG-16-TT概述

Clock Generator, 20MHz, CMOS, PDSO16, 4.40 MM, GREEN, TSSOP-16

ASM3P622S00EG-16-TT规格参数

参数名称属性值
包装说明4.40 MM, GREEN, TSSOP-16
Reach Compliance Codeunknown
JESD-30 代码R-PDSO-G16
长度5 mm
端子数量16
最高工作温度70 °C
最低工作温度
最大输出时钟频率20 MHz
封装主体材料PLASTIC/EPOXY
封装代码TSSOP
封装形状RECTANGULAR
封装形式SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
主时钟/晶体标称频率20 MHz
认证状态Not Qualified
座面最大高度1.2 mm
最大供电电压3.6 V
最小供电电压3 V
标称供电电压3.3 V
表面贴装YES
技术CMOS
温度等级COMMERCIAL
端子形式GULL WING
端子节距0.65 mm
端子位置DUAL
宽度4.4 mm
uPs/uCs/外围集成电路类型CLOCK GENERATOR, OTHER
Base Number Matches1

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ASM3P622S00B/E
Low Frequency Timing-Safe™
Peak EMI Reduction IC
General Features
Low Frequency Clock distribution with Timing-Safe™
Peak EMI Reduction
Input frequency range: 4MHz - 20MHz
2 different Spread Selection options
Spread Spectrum can be turned ON/OFF
External Input-Output Delay Control option
Supply Voltage: 3.3V±0.3V
Commercial and Industrial temperature range
Packaging Information:
ASM3P622S00B: 8 pin SOIC, and TSSOP
ASM3P622S00E:16 pin SOIC, and TSSOP
The First True Drop-in Solution
ASM3P622S00B/E operates from a 3.3V supply and is
available in two different packages, as shown in the
ordering information table, over commercial and Industrial
temperature range.
one reference input and drives out eight low-skew Timing-
Safe™ clocks.
ASM3P622S00B/E has an SS% that selects 2 different
Deviation and associated Input-Output Skew (TSKEW).
Refer to
Spread Spectrum Control
and
Input-Output Skew
table for details.
ASM3P622S00E has a CLKOUT for adjusting the Input-
Output clock delay, depending upon the value of capacitor
connected at this pin to GND.
Functional Description
ASM3P622S00B/E is a versatile, 3.3V Zero-delay buffer
designed to distribute low frequency Timing-Safe™ clocks
with Peak EMI reduction. ASM3P622S00B is an eight-pin
version, accepts one reference input and drives out one
low-skew Timing-Safe™ clock. ASM3P622S00E accepts
Application
ASM3P622S00B/E is targeted for use in Displays and
memory interface systems.
General Block Diagram
DLY_CTRL
VDD
SS%
CLKIN
PLL
CLKOUT(s)*
(Timing-Safe™)
*For
ASM3P622S00E -
8 CLKOUTS
SSON
GND
©2010 SCILLC. All rights reserved.
JANUARY 2010 – Rev. 1
Publication Order Number:
ASM3P622S00/D

 
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