TH3122
K-Bus Transceiver with integrated Voltage Regulator
Features and Benefits
K-Bus Transceiver:
PNP-open emitter driver with slew rate control and current limitation
BUS input voltage -24V ... 30V (independently of V
S
)
ISO 9141 and ODBII compliant
Possibility of BUS wake up
Operating voltage V
S
= 5.5 ... 16 V
Very low standby current consumption <100
µ
A
in normal mode (< 50
µ
A in sleep mode)
Linear low drop voltage regulator:
Output voltage 5V± 2%
Output current max. 100mA
Output current limitation
Overtemperature shutdown
Pin Diagram
SOIC16
VS
EN
VTR
GND
GND
BUS
SI
SO
1
16
VCC
SENSE
RESET
GND
GND
TxD
RxD
SEN/STA
2
15
3
14
4
13
TH3122
5
12
6
11
7
10
8
9
Configurable reset time (15ms/100ms) and reset threshold voltage (3.15V / 4.65V)
Low voltage detection at VS
Wake-up by K-BUS traffic and start-up capable independent of EN voltage level
Universal comparator with an input voltage range –24V … 30V and digital output
Load dump protected (40V)
Ordering Information
Part No.
TH3122
Temperature Code
K ( -40ºC to 125ºC )
Package Code
DF ( SOIC16, 300mil )
General Description
The TH3122 consists of a low drop voltage
regulator 5V/100mA and a K-Bus transceiver. The
transceiver is suitable for K-Bus systems conform
to ISO 9141.
The combination of voltage regulator and bus
transceiver in combination with the monitoring
functions make it possible to develop simple, but
powerful and cheap nodes in K-Bus systems.
The wide output current area and the configurable
reset time and reset voltage works together with
many different microcontrollers.
3901003122
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TH3122
K-Bus Transceiver with integrated Voltage Regulator
Functional Diagram
VS
Power Supply
VCC
Over Temp
EN
+5V
7.8V
6.8V
+5V
SENSE
Reset-Logic
VTR
VTR-Logic
RESET
OSC
Wake-up
V
thH
V
thL
RxD
BUS
Bus-Logic
pnp Control
slew rate
foldback
+5V
TxD
SEN/STA
SI
V
THSI_H
V
THSI_L
SO
Figure 1 - Block Diagram
3901003122
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TH3122
K-Bus Transceiver with integrated Voltage Regulator
Functional Description
The TH3122 consists of a voltage regulator 5V/100mA
and a K-Bus transceiver, which is a bi-directional bus
interface device for data transfer between K-Bus and the
K-Bus protocol controller.
to Wake-up
Logic
Also integrated into the transceiver are a voltage and
time controlled reset management, power down, wake
up function and a universal comparator for extended
applications.
t
debWake
t
debBUS
RxD
POR
VBAT
POR
VCC
Control-
logic
Bit-Compare
Constant-Low
V
thH
V
thL
VCC
pnp-
Control
- slew rate
- I
B
- foldback
BUS
TxD
ESD
VCC
OSC
Vref
Biasing
SENSE
ESD
Figure 2 - Block Diagram K-Bus Transceiver
K-BUS Interface
The BUS Interface builds the connection between the
serial 5V bus line of the protocol controller and the 12V
K-Bus line.
The transceiver consists of a pnp-driver with slew rate
control and fold-back characteristic and contains also in
the receiver a high voltage comparator followed by a
debouncing unit.
electromagnetic emission of the bus line, the TH3122
has an integrated slew rate control.
Receive Mode
The data at the pin BUS will be transferred to the pin
RxD. Short spikes on the bus signal are suppressed by
the implemented debouncing circuit.
BUS
Transmit Mode
During the transmission the data at the pin TxD will be
transferred to the pin BUS. To minimize the
< t
debH
< t
debL
SEN/STA
RxD
t
debH
t
debL
TxD
Figure 4 - Receive Mode Pulse Diagram
BUS
Figure 3 - Transmit Mode Pulse Diagram
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TH3122
K-Bus Transceiver with integrated Voltage Regulator
Bit Compare
If the signals at the pin TxD and the pin BUS within
a specified time t
bc
are not identical, the
transmission will be interrupted.
If both signals at TxD and BUS are “High” within
the time t
ena
the transmission will be enabled. The
bit-compare-function is active when the pin SEN/
STA is open (not overwritten).
Using this pin as an input the transmission path
can be overwritten (independent of bit-compare
and constant-low function):
SEN/STA=”0”
forcing the transmission path free
SEN/STA=”1”
disable the transmission path
Constant Low Switch Off
A falling edge at pin TxD (from “1” to “0”) starts the
internal constant low timer (SEN/STA open).
If the low level “0” is valid for the time t
low
the
transmission unit of the TH3122 will be disabled.
The receive unit is still active. A high level “1” at
TxD with a minimum pulse width of t
rec
resets the
constant low timer.
Transmitting is not possible until TxD and BUS is
High for the time t
ena
.
t < t
rec
Figure 5 - Bit Compare Pulse Diagram
SEN/STA
The pin SEN/STA is bidirectional. Used as an
output the pin indicates whether the transmit-path
is enabled or disabled:
SEN/STA =”0”
transmission path is enabled
SEN/STA =”1”
transmission path is disabled
TxD
SEN/STA
t
low
t
ena
Figure 6 - Constant Low Pulse Diagram
Linear Regulator and Controlling Functions
Regulator
The TH3122 has an integrated linear regulator with an
output voltage of 5V ±2% and an output current of max.
100mA. The regulator is switched on or off with a signal
on the EN pin or wakes up with a BUS signal.
voltage level on the VTR pin (see table VTR
Programming). After t
RES
a rising edge on the RESET
output is generated (see figure 7 - Initialization).
The regulator is active and can only be switched off with
a falling edge on EN. The regulator remains with
EN=high in active mode and therefore the V
CC
voltage is
also active.
Initialization
The initialization is started if the power supply is switched
on, or after the temperature limitation has switched off
the regulator or in case of BUS traffic (wake up).
If the V
CC
voltage level is higher than V
RESEIN
, the reset
time t
RES
is started. This reset time is determined by the
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TH3122
K-Bus Transceiver with integrated Voltage Regulator
VTR-Mode
VS
V
RES
V
RES
= V
RES1
= 3.15V
V
RES
= V
RES2
= 4.65V
V
RES
= V
RES1
= 3.15V
V
RES
= V
RES2
= 4.65V
t
Res
100ms
100ms
15ms
15ms
VTR = GND
VTR = VCC
V
RESEIN
VCC
t
Res
V
RES1/2
t
rr
VTR with R
≥
50k
Ω
to GND
VTR with R
≥
50k
Ω
to VCC
RESET
VTR-Programming
The voltage on VTR input is read out if the voltage at this
pin is higher than V
RESEIN
. This value defines the reset
switch off voltage V
RES
. With the next oscillator cycle it
switches on the pull up current source if VTR=low or the
pull down current source if VTR=high. The sources are
active for one oscillator cycle. The level changes during
this procedure on VTR, which depends on the external
pull up or pull down resistors control the reset time t
Res
Figure 7 - Initialization
The input EN has an internal pull down resistor. If
EN=high, the internal pull down current is switched off to
minimize the quiescent current.
RESET Output
The RESET output is switched from low to high if V
S
is
switched on and V
CC
>V
RESEIN
after the time t
RES
.
If the voltage V
CC
drops below V
RES1
or V
RES2
then the RESET
output is switched from high to low after the time t
rr
has been
reached.
The voltage level for V
RES1
and V
RES2
and the
corresponding times t
RES
can be programmed via the
analogue input VTR.
Temperature Limitation
If the junction temperature 150ºC < T
j
< 170ºC the over
temperature recognition will be active and the regulator
voltage and the BUS driver will be switched off. After T
j
falls below 140ºC the TH3122 will be initialized,
independently of the voltage levels on EN and BUS.
The function of the TH3122 is possible between T
Amax
and the switch off temperature, but small parameter
differences can appear.
Wake up with BUS traffic
If the regulator is put in standby mode it can be woken
up with the BUS interface. Every pulse on the BUS (high
pulse or low pulse) with a pulse width of min. 45
µ
s will
switch on the regulator.
After the BUS has woken up the regulator, it can only be
switched off with a high level followed by a low level on
the EN pin.
Low Voltage Detection V
S
Low voltage on V
S
is monitored on SENSE output.
If V
S
has reached the level of V
S
=6.8V then the SENSE
output generates low level. The normal
operating range is V
S
> 7.8V and the SENSE output
generates a high level.
Reset Programming on VTR
With the VTR pin the reset switches off levels and delay
time can be programmed.
The voltage on VCC influences the reset function.
Universal Comparator
The TH3122 consist of a universal comparator for
general use. The positive input of this comparator is
connected to the pin SI. The input voltage range of SI is
0V...V
S.
The input voltage is compared with a fixed
reference voltage at high or low level and the comparator
output SO drives a 5V digital signal.
3901003122
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