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BU-61559 SERIES
MIL-STD-1553B NOTICE 2 AIM-HY’ER
FEATURES
•
Complete Integrated 1553B Notice 2
Interface Terminal
•
Direct Replacement for BUS-61559
AIM-HY’er Series
•
Functional Superset of BUS-61553
AlM-HY Series
•
Internal Address and Data Buffers for
Direct Interface to Processor Bus
•
RT Subaddress Circular Buffers to
Support Bulk Data Transfers
•
Optional Separation of RT Broadcast
Data
DESCRIPTION
DDC’s BU-61559 series of Advanced Integrated Mux Hybrids with
enhanced RT Features (AIM-HY’er) comprise a complete interface
between a microprocessor and a MIL-STD-1553B Notice 2 bus,
implementing Bus Controller (BC), Remote Terminal (RT), and
Monitor Terminal (MT) modes. Packaged in a single 78-pin DIP or flat
package, the BU-61559 series contains dual low-power transceivers
and encoder/decoders, complete BC/RT/MT protocol logic, memory
management and interrupt logic, 8K x 16 of shared static RAM, and
a direct, buffered interface to a host processor bus.
The BU-61559 includes a number of advanced features that support
MIL-STD-1553B Notice 2 and STANAG 3838. Other salient features
of the BU-61559 serve to provide the benefits of reduced board space
requirements, enhanced software flexibility, and reduced host proces-
sor overhead.
The BU-61559 contains internal address latches and bidirectional
data buffers to provide a direct interface to a host processor bus.
Alternatively, the buffers may be operated in a fully transparent mode
in order to interface to up to 64K words of external shared RAM
and/or connect directly to a component set supporting the 20 MHz
STANAG 3910 bus.
The memory management scheme for RT mode provides an option
for separation of broadcast data, in compliance with 1553B Notice 2.
A circular buffer option for RT message data blocks offloads the host
processor for bulk data transfer applications.
The BU-61559 series hybrids operate over the full military tempera-
ture range of -55 to +125°C and MIL-PRF-38534 processing is avail-
able. The hybrids are ideal for demanding military and industrial
microprocessor-to-1553 applications.
•
Internal Interrupt Status and Time Tag
Registers
•
Internal Command Illegalization
•
MIL-PRF-38534 Processing Available
•
Transmitter Inhibit Control for
Individual Bus Channels
FOR MORE INFORMATION CONTACT:
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
Technical Support:
1-800-DDC-5757 ext. 7771
©
2002 Data Device Corporation
Data Device Corporation
www.ddc-web.com
ILLEGALLIZATION
LOGIC
8K x 16
DUAL
PORT
RAM
CLK IN (16MHz)
LOW-POWER
TRANSCEIVER
A
DUAL
ENCODER/
DECODER
BC/RT/MT
PROTOCOL
MEMORY DATA
DATA
BUFFERS*
D15-D∅
(PROCESSOR
DATA)
(ILLEGALIZATION ILLENA
ENABLE)
BUS-25679
8
1
7
2
5
4
3
TX_INH_A
A15-A∅
(PROCESSOR
ADDRESS)
2
MEMORY ADDRESS
RTAD 4-∅, RTADP
BRO_ENA
RTFAIL
RTFLAG
BCSTRCV, CMD_STR, TXDTA_STR
RXDTA_STR, MSG_ERR, INCMD
BUS-25679
8
1
7
2
5
4
3
LOW-POWER
TRANSCEIVER
A
ADDRESS
LATCHES/
BUFFERS*
ADDR_LAT
(ADDRESS
LATCH
CONTROL)
TX_INH_A
(RT ADDRESS)
TRANSPARENT/BUFFERED, MSTCLR,
STRBD, SELECT, MEM/REG, RD/WR
(PROCESSOR
CONTROL)
(INTERRUPT
REQUEST)
(MEMORY
CONTROL)
(SUBSYSTEM
FLAG)
(TIME TAG
CLOCK)
(BROADCAST
ENABLE)
(RTFAIL,
RTFLAG)
(BROADCAST,
MESSAGE
TIMING, DATA
STROBE AND ERROR
INDICATORS)
MEMORY
IOEN, READYD
MANAGEMENT,
INT
SHARED
MEMEN-OUT,MEMWR, MEMOE
RAM/
PROCESSOR
MEMENA-IN
INTERFACE,
SSFLAG
INTERRUPT
LOGIC
TAGCLK
BU-61559 Series
E-03/06-0
FIGURE 1. BU-61559 BLOCK DIAGRAM
TABLE 1. BU-61559 SPECIFICATIONS
PARAMETER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
• Logic +5V
• Transceiver +5V
• -15V (BU-61559X1)
• -12V (BU-61559X2)
Receiver Differential Voltage
Logic
• Voltage Input Range
RECEIVER
Differential Input Voltage
Differential Input Resistance (see
notes 1-6)
Differential Input Capacitance (see
notes 1-6)
Threshold Voltage, Transformer cou-
pled, measured on stub
CMRR
• (BU-61559X1, through BUS-25679
transformer at 1MHz)
• (BU-61559X2, through BUS-29854
transformer at 1MHz)
TRANSMITTER
Differential Output Voltage
• Direct coupled across 35 Ohms,
measured on bus
• Transformer coupled, measured on
stub (for 20 Vp-p min. stub voltage,
consult factory)
For -601 Reliability Grade (note 7)
Output noise, differential (direct cou-
pled)
Output offset Voltage, direct coupled
across 35 Ohms
Rise/Fall time
LOGIC
Vih
Vil
Iih (Vcc = 5.5V, Vih = 2.7V)
• D15 through D0, A15 through A0,
MEM/REG, STRBD, RD/WR,
MSTCLR, SELECT, TX_INH_A,
TX_INH_B, SSFLAG,
TRANSPARENT/BUFFERED,
ADDR_LAT, TAGCLK
RTAD4 through RTAD0, RTADP
BRO_ENA, RTFLAG, ILLENA
MEMENA-IN, CLK_IN
Iil (Vcc = 5.5V, Vil = 0.4V)
• D15 through D0, A15 through A0,
MEM/REG, STRBD, RD/WR,
MSTCLR, SELECT, TX_INH_A,
TX_INH_B, SSFLAG,
TRANSPARENT/BUFFERED,
ADDR_LAT, TAGCLK
RTAD4 through RTAD0, RTADP
BRO_ENA, RTFLAG, ILLENA
MEMENA-IN, CLK_IN
UNITS
VALUE
TABLE 1. BU-61559 SPECIFICATIONS (CONT)
PARAMETER
LOGIC (CONT)
Voh (Vcc=4.5V, Vih=2.7V, Vil=0.4V)
• (Ioh=-6.8 mA)
D15 through D0, A15 through A0
• (Ioh=-3.4 mA)
MEMOE, MEMENA-OUT,
MEMWR, INT, IOEN, READYD
• (Ioh=-0.4 mA)
RTFAIL, INCMD, BCSTRCV,
MSG_ERR, CMD_STR,
TXDTA_STR, RXDTA_STR
VoL (Vcc=4.5V, Vih=2.7V, Vil=0.4V)
• (Iol=-6.8 mA)
D15 through D0, A15 through A0
• (Iol=2.0 mA)
RTFAIL, INCMD, BCSTRCV,
MSG_ERR, CMD_STR
• (Iol=3.4 mA)
MEMOE, MEMENA-OUT,
MEMWR, INT, IOEN, READYD
• (Iol=4.0 mA)
TXDTA_STR, RXDTA_STR
Ci (f=1 MHz)
Co (f=1 MHz)
Cio (f=1 MHz)
D15 through D0, A15 through A0
POWER SUPPLY REQUIREMENTS
Voltages/Tolerances
• +5V (Logic)
• +5V (Ch A, Ch B)
• -15V (BU-61559X1)
• -12V (BU-61559X2)
Current Drain
• +5V
• -15V (BU-61559X1)
Idle
25% Duty Cycle
50% Duty Cycle
100% Duty Cycle
• -12V (BU-61559X2)
Idle
25% Duty Cycle
50% Duty Cycle
100% Duty Cycle
POWER DISSIPATION
Total Hybrid
• BU-61559X1
Idle
25% Duty Cycle
50% Duty Cycle
100% Duty Cycle
• BU-61559X2
Idle
25% Duty Cycle
50% Duty Cycle
100% Duty Cycle
UNITS
VALUE
V
V
V
V
Vp-p
V
-0.5 to 7.0
-0.5 to 7.0
+0.3 to -18.0
+0.3 to -18.0
40 max
-0.5 to 7.0
V
V
3.7 min
3.7 min
V
2.4 min
Vp-p
k Ohms
pF
Vp-p
40 max
11 min
10 max
0.70 min, 0.86 max
V
V
0.4 max
0.4 max
V
0.4 max
dB
dB
50 min
50 min
V
pF
pF
pF
0.4 max
50 max
10 max
50 max
(see note 7)
Vp-p
Vp-p
6 min., 9 max
18 min, 20 typ, 27 max
Vp-p
mVp-p,
diff
V
ns
20 min, 21 typ, 27 max
10 max.
±90 max
100 min, 150 typ,
300 max
2.0 min
0.8 max
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
4.5 min, 5.5 max
4.5 min, 5.5 max
-15.75 min, -14.25 max
-12.6 min, -11.4 max
85 typ, 170 max
5 min, 40 typ, 80 max
25 min, 80 typ, 130 max
45 min, 120 typ, 180 max
85 min, 200 typ, 280 max
5 min, 40 typ, 80 max
25 min, 90 typ, 135 max
45 min, 135 typ, 185 max
85 min, 230 typ, 305 max
(see note 7)
V
V
µA
-346 min, -42 max
W
W
W
W
W
W
W
W
1.025 typ, 2.050 max
1.325 typ, 2.500 max
1.625 typ, 2.950 max
2.225 typ, 3.850 max
0.905 typ, 1.810 max
1.025 typ, 2.170 max
1.445 typ, 2.470 max
1.985 typ, 3.310 max
µA
-397 min, -50 max
Data Device Corporation
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3
BU-61559 Series
E-03/06-0
TABLE 1. BU-61559 SPECIFICATIONS (CONT)
PARAMETER
POWER DISSIPATION (CONT)
Hottest Die
• BU-61559X1
Idle
25% Duty Cycle
50% Duty Cycle
100% Duty Cycle
• BU-61559X2
Idle
25% Duty Cycle
50% Duty Cycle
100% Duty Cycle
CLOCK INPUT
Frequency
• Nominal Value
• Long Term Tolerance
• Short Term Tolerance, 1 second
• Duty Cycle
1553 MESSAGE TIMING
Completion of CPU Write (BC Start)-
to Start of first BC Message
BC Intermessage Gap
BC Response Timeout
RT Response Time
Rt-to RT Timeout (Mid-Parity of
Transmit Command to Mid-Sync of
Transmitting RT Status)
Transmitter Watchdog Timeout
THERMAL
Thermal Resistance, Junction-to-case,
Hottest Die (
JC
)
Thermal Resistance, Case-to-ambient,
Hottest Die (
CA
)
Operating Junction Temperature
Operating Case Temperature
• -B, -M
• -(blank)
Storage Temperature
Lead Temperature
(soldering, 10 seconds)
PHYSICAL CHARACTERISTICS
Size
• 78-pin Ceramic QIP
• 78-pin Ceramic Flat Pack
• Weight
UNITS
VALUE
FUNCTIONAL OVERVIEW
GENERAL (REFERENCE BLOCK DIAGRAM FIGURE 1)
The BU-61559 Advanced Integrated Multiplex Hybrid with
enhanced RT features (AIM-HY'er) comprises a complete interface
between a host microprocessor bus and a dual redundant MIL-
STD-1553B Notice 2 bus. The hybrids are comprised of dual low-
power transceivers and encoder/decoders, full BC/RT/MT protocol,
memory management logic, 8K words of internal shared RAM, and
a direct, internally buffered processor interface. The BU-61559 is
packaged in a four square inch hybrid package and is available in
both plug-in and surface mountable (flatpack) packages.
W
W
W
W
W
W
W
W
0.45 typ, 0.68 max
0.65 typ, 1.06 max
0.875 typ, 1.45 max
1.30 typ, 2.23 max
0.39 typ, 0.59 max
0.60 typ, 0.98 max
0.81 typ, 1.36 max
1.30 typ, 2.16 max
TRANSCEIVERS
MHz
%
%
%
µS
µS
µS
µS
µS
16.0
±0.1
±0.01
33 min, 67 max
5.85 min, 7.21 max
13.98 min, 17.82max.
17.5 min, 19.0 typ,
22.5 max
9.8 min, 10.9 typ,
11.7 max
18.0 min, 18.75 typ,
19.5 max
768 typ
6.13
10.5
-55 to +160
-55 to +125
0 to +70
-65 to +150
+300
The transceiver front end of the BU-61559 AIM-HY'er hybrids is
implemented by means of low-power bipolar analog monolithic
and thick-film hybrid technology. The transceiver requires +5 V
and -15V or -12V only (no +15 V or +12V is required) and include
voltage source transmitters. The voltage source transmitters pro-
vide superior line driving capability for long cables and heavy
amounts of bus loading. In addition, the monolithic transceivers
may be modified to provide a minimum stub voltage of 20Vp-p,
as required for MIL-STD-1760 applications. Consult the factory
for additional information.
The receiver sections of the BU-61559 are fully compliant with
MIL-STD-1553B in terms of front end overvoltage protection,
threshold, common mode rejection, and word error rate. In addi-
tion, the receiver filters have been designed for optimal operation
with the BU-61559's 16 MHz Manchester II decoders.
µS
°C/W
°C/W
°C
°C
°C
°C
°C
MIL-STD-1553 PROTOCOL
The 1553 protocol section of the BU-61559 includes dual
encoder/decoders and complete registers, word count, timing,
and sequencing logic for Bus Controller (BC), Remote Terminal
(RT), and Monitor Terminal (MT) modes. The dual Manchester II
decoders utilize a 16 MHz sampling clock, providing superior
performance in terms of word error rate and tolerance to zero-
crossing distortion. The encoder section of the protocol logic
includes a transmitter watchdog timer. The watchdog timer mon-
itors the digital encoder outputs and serves to inhibit the trans-
mitters after a period of 768 µs.
The BC protocol supports all MIL-STD-1553B formats, complete error
detection, and multi-message frames of up to 64 unique messages.
Protocol for RT mode supports all message formats and dual
redundant 1553B mode codes. The BU-61559 has passed the
RT Validation Test Plan at SEAFAC; this test encompasses the
dual transceiver and all of the RT protocol logic.
The Monitor (MT) protocol of the BU-61559 monitors both 1553
buses. For each word received from either bus, both the 16 bits
of word data plus a 16-bit Identification Word (“Tag” Word) are
stored in the AIM-HY'er memory space.
BU-61559 Series
E-03/06-0
in.
(mm.)
in.
(mm.)
oz.
(g)
1.80 x 2.10 x 0.21
(45.7 x 53.3 x 5.3)
1.80 x 2.10 x 0.21
(45.7 x 53.3 x 5.3)
1.7
(48.2)
Notes:
The following notes are applicable to the Receiver Differential Resistance
and Differential Capacitance specifications:
(1) Specifications include both transmitter and receiver (tied together internally).
(2) Impedance parameters are specified directly between pins TX/RX A(B) and
TX/RX A(B) of the BU-61559 hybrid.
(3) It is assumed that all power and ground inputs to the hybrid are connected and
that the hybrid case is connected to ground for the impedance measurement.
(4) The specifications are applicable for both unpowered and powered conditions.
(5) The specifications assume a 2 Vrms balanced, differential, sinusoidal input.
The applicable frequency range is 75 kHz to 1 MHz.
(6) Minimum resistance and maximum capacitance parameters are guaranteed
over the operating range, but are not tested.
(7) -601 Power Supply Requirements and Power Dissipation values will be higher.
Data Device Corporation
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4
ADVANCED FEATURES
While maintaining functional and software compatibility to the
previous generation BUS-61553 series AIM-HY hybrids, the BU-
61559 incorporates a number of advanced features to support
1553B Notice 2. Other enhancements provided by the BU-61559
serve to provide the benefits of reduced board space require-
ments, expanded software flexibility, and reduced host processor
overhead.
external PROM, PLD, or RAM device. The illegalization architec-
ture allows for any subset of the 4096 possible combinations of
broadcast/own address, T/R bit, subaddress, and word
count/mode code to be illegalized. The BU-61559 illegalization
scheme is under software control of the host processor. As a
result, it is inherently self-testable.
INTERNAL TIME TAG
The BU-61559 includes an internal read/write Time Tag Register.
INTERNAL TRI-STATE BUFFERS
The BU-61559 contains internal address latches and bidirection-
al data buffers to provide a direct interface to either a multiplexed
or a non-multiplexed processor bus. Alternatively, the latches and
buffers may be operated in a fully transparent mode to interface
to up to 64K words of external shared RAM and/or a component
set supporting the STANAG 3910 20 MHz data bus.
This register is a CPU read/write 16-bit counter with a program-
mable resolution of either 2, 4, 8, 16, 32, or 64 µs per LSB. The
Time Tag Register may also be clocked from an external oscilla-
tor. Another option allows the Time Tag Register to be incre-
mented under software control. This supports self-test for the
Time Tag Register.
For each message processed, the value of the Time Tag register
is loaded into the second location of the respective descriptor
stack entry (“TIME TAG WORD”) for both BC and RT modes.
Additional options are provided to clear the Time Tag Register
following a Synchronize (without data) mode command or load
the Time Tag Register following a Synchronize (with data) mode
command. Another option enables an interrupt request and a bit
in the Interrupt Status Register to be set when the Time Tag
Register rolls over from 0000 to FFFF. Assuming the Time Tag
Register is not loaded or reset, this will occur at approximately 4-
second time intervals for 64 µs/LSB resolution, down to 131 ms
intervals for 2 µs/LSB resolution.
Another programmable option for RT mode is for the Service
Request Status Word bit to be automatically cleared following the
BU-61559's response to a Transmit Vector Word mode command.
MEMORY MANAGEMENT
The BU-61559 incorporates complete memory management and
processor interface logic. The software interface to the host
processor is implemented by means of eight internal registers plus
a 64K word shared RAM address space, which generally includes
the 8K words of internal RAM. For all three modes, a stack area of
RAM is maintained. In BC mode, the stack allows for the schedul-
ing of multi-message frames. For all three modes, the stack pro-
vides a real time chronology of all messages processed. In addi-
tion to the stack processing, the memory management logic per-
forms storage, retrieval, and manipulation functions involving
pointer and message data structures for all three modes.
The BU-61559 provides a number of programmable options for
RT mode memory management. In compliance with MIL-STD-
1553B Notice 2, received data from broadcast messages may be
optionally separated from non-broadcast received data. For each
transmit, receive or broadcast subaddress, either a single-mes-
sage data block or a variable-sized (128 to 8192 words) circular
buffer may be allocated for data storage. In addition to helping
ensure data consistency, the circular buffer feature provides a
means of greatly reducing host processor overhead for bulk data
transfer applications. End-of-message interrupts may be enabled
either globally, following error messages on a Tx/Rx/Bcst-subad-
dress basis, or when any particular Tx/Rx/Bcst-subaddress circu-
lar buffer reaches its lower boundary. In addition to interrupts for
RT subaddress and circular buffer rollover conditions, the proces-
sor interface logic provides maskable interrupts and a 9-bit
Interrupt Status Register for end of message, end of BC message
list, erroneous messages, Status Set (BC mode), Time Tag
Register Rollover, and RT Address Parity Error conditions. The
Interrupt Status Register allows the host processor to determine
the cause of all interrupts by means of a single READ operation.
INTERFACE TO STANAG 3910 20 MHZ FIBER OPTIC BUS
For applications requiring a higher rate of data transfer than MIL-
STD-1553's 1 Mbps, it is possible to interface the BU-61559
directly to a component set supporting STANAG 3910. A
STANAG 3910 bus operates as an adjunct to, and is controlled
by, a MIL-STD-1553B Notice 2 (STANAG 3838) bus. The
STANAG 3910 standard defines a Manchester II encoded serial
data bus with a data rate of 20 Mbps, allowing for both electrical
and fiber optic implementations. STANAG 3910 is intended for
high-speed bulk data transfers, supporting message lengths of
up to 4096 words.
CLOCK INPUT
The BU-61559 requires an external 16 MHz clock input. All inter-
nal timing is derived from this clock. Refer to FIGURE 1 for the
short-term and long-term accuracy requirements of the input
clock frequency.
INTERNAL COMMAND ILLEGALIZATION
The BU-61559 implements internal command illegalization for
RT mode. The internal illegalization eliminates the need for an
Data Device Corporation
www.ddc-web.com
5
BU-61559 Series
E-03/06-0
FPGA/CPLD
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