CA20C03A
DES ENCRYPTION PROCESSOR
• The CA20C03A is an improved version of the
DES encryption processor designed by Tundra
Semiconductor Corporation.
• Data transfer rates up to 3.85 Mbytes per second
• Encrypt and decrypt using Data Encryption
Standard (DES) adopted by the U.S. Department
of Commerce, National Bureau of Standards
(NBS) - publication FIPS PUB 46 (1-15-1977)
• Validated by the National Institute for Standards
and Technology (NIST) in accordance with the
procedures specified in NBS publication 500-20
• Electronic Code Book (ECB) and Cipher Block
Chaining (CBC)
• Encrypt and decrypt 64-bit data words using 56-
bit key words
• Parity check on key word loading
• Key stored in device is not externally accessible
• Standard 8-bit microprocessor interface
• Battery Back-up capability of internal key
register
• Low power CMOS with TTL I/O compatibility
• Available in PLCC, PDIP, and TQFP packages
The Tundra Semiconductor Corporation CA20C03A
DES
Encryption Processor
is designed to encrypt and decrypt 64-
bit blocks of data using the algorithm specified in the Federal
Information Processing Data Encryption Standard -
publication FIPS PUB 46 (1-15-1977). DES is the standard
data encryption algorithm used for file and communications
encryption, and as such is widely established in the security,
Table 3-1 : CA20C03A Transfer Rates
Product Code
Data Transfer Rates - ECB Mode
(Mbytes per Second)
System Clock
finance and banking industries. The CA20C03A encrypt 64-
bit clear text words using 56-bit, user-specified keys to
produce 64-bit cipher text words. When reversed, the cipher
text words are decrypted to produce the original clear text
words.
If your application requires strictly WD2001 mode then
please contact the factory for documentation.
The CA20C03A is implemented in low power CMOS
technologies with TTL compatible I/O. It is offered in 28-pin
PDIP, 28-lead PLCC, and 44-pin TQFP packaging.
Application areas for the CA20C03A DES chip spans a
diverse industrial base of financial, information processing,
telecommunications and data communications companies.
•
•
•
•
•
•
•
3
3.1
Secure Brokerage transactions
Electronic fund transfers
Secure banking/business accounting
Mainframe communications
Remote and host computer communications
Secure disk or magnetic tape data storage
Secure packet-switching transmission
Data Encryption Products
CA20C03A&W
CA20C03A-5
CA20C03A-10
CA20C03A-16
CA20C03A-20
CA20C03A-25
0.77
1.54
2.46
3.08
3.85
5 MHz
10 MHz
16 MHz
20 MHz
25 MHz
Warning:
These devices cannot be shipped outside North America without written authorization from Canadian External Affairs and Department of National
Defence or the US State Department and Department of Defence.
Tundra Semiconductor Corporation
3-1
CA20C03A
Tundra Semiconductor Corporation
TO SYSTEM BUS
DAL 0
.
.
DAL 7
8–BIT DAL BUS (Bits 0 – 7)
COMMAND
REGISTER
STATUS
REGISTER
PARITY
DETECT
KEY REGISTER
(56 BITS)
DATA REGISTER
(64 BITS)
IV REGISTER
(64 BITS)
MASTER CONTROL
STATIC KEY
REGISTER
(56 BITS)
STATIC DATA
REGISTER
(64 BITS)
TEMP REGISTER
(64 BITS)
NBS ALGORITHM
INTERFACE CONTROL
V
DD
V
SS
CLK
MR
CS
WE
RE
A1
A0
KPE
KR
IVIR
SPIR
DIR
DOR
ACT
E/D
BB
CBC/ECB
CRPS
Figure 3-1 : CA20C03A Block Diagram
3-2
Tundra Semiconductor Corporation
Tundra Semiconductor Corporation
CA20C03A
A1,O/N
BB
1
CBC/EBC
IVIR
SPIR
V
DD
A1,O/N
WE
RE
CLK
CS
DAL1
DAL3
DAL5
DAL7
E/D
3
4
5
6
7
8
9
10
11
12
13
14
26
25
24
23
22
21
20
19
18
17
16
15
25 24 23 22 21 20 19
MR
2
27
CRPS
KPE
ACT
A0, NK
1
28
a) 28-pin PDIP
b) 28-pin PLCC
CBC/EBC
SPIR
DOR
IVIR
N/C
N/C
N/C
BB
1
DIR
N/C
V
DD
A1,O/N
N/C
N/C
N/C
N/C
WE
RE
CLK
CS
DAL1
44 43 42 41 40 39 38
1
2
3
4
5
6
7
8
9
10
11
37 36 35 34
33
32
31
30
KR
V
SS
(GND)
N/C
E/D
N/C
ACT
KPE
N/C
MR
CRPS
A0, NK
DAL6
CA20C03A
29
28
27
26
25
24
23
12 13 14 15 16 17 18 19 20 21 22
DAL3
DAL7
DAL0
DAL2
DAL4
N/C
DAL5
N/C
N/C
c) 44-pin TQFP
Figure 3-2 : CA20C03A Pin Configuration
Tundra Semiconductor Corporation
N/C
N/C
DAL1
DOR
DIR
KR
V
SS
(GND)
E/D
ACT
KPE
MR
CRPS
A0, NK
DAL6
DAL4
DAL2
DAL0
V
SS
(GND)
KR
DIR
DOR
BB
1
CBC/EBC
IVIR
SPIR
26
27
28
1
2
3
4
5
6
7
8
9
10 11
18
17
16
DAL6
DAL4
DAL2
DAL0
DAL7
DAL5
DAL3
WE
RE
CLK
V
DD
CS
CA20C03A
CA20C03A
15
14
13
12
3-3
CA20C03A
Tundra Semiconductor Corporation
Table 3-2 : Pin Description
Pin
Symbol
PLCC
A0, NK
19
Type
PDIP
19
Name and Function
Address 0, New Key:
When
CRPS
is logic 1 or open, a high on this input addresses the
Command or Status Register (see Table 3-18).
When
CRPS
and A1, O/
N
are logic 0, a high on this input requests that a new key be loaded in
the Key Register. Device responds by activating the KR pin.
TQFP
24
I
A1, O/
N
6
6
2
I
Address 1, Old/New:
When
CRPS
is logic 1 or open, and this input is logic 1, the Status
Register is addressed (
CS
= 0, A0 = 1). When this input is logic 0, the Command Register is
addressed (
CS
= 0, A0 = 1). This input is ignored when A0 = 0. Note that this input has an
internal pull-up resistor.
When
CRPS
is logic 0 (low) and this input is logic 0, the device is in CA20C03A mode. When
this input is logic 1, the device is in WD2001 mode. The only way to return to CA20C03A mode
from WD2001 mode is to reset the device.
Caution: In WD2001 mode, pin 6 of the CA20CO3A device must not be connected to +12V as it
will irreparably damage the device.
ACT
23
23
29
I/O
Activate:
When
CRPS
is logic 1 or open, this pin is an output reflecting the status of the
Activate
bit (bit 1) of the Command Register.
When
CRPS
is logic 0, this pin is an input that overrides the Activate bit of the Command
Register.
BB
1
1
40
I/O
Battery Back-up Key:
When
CRPS
is logic 1 (open), this pin is an output reflecting the status
of the
battery back-up key
bit (bit 5) of the Command Register. When
CRPS
is logic 0 or low,
this pin is an input that overrides the
battery back-up key
bit.
Cipher Block Chaining/Electronic Code Book:
When
CRPS
is logic 1 or open, this pin is an
output pin reflecting the status of CBC/
ECB
bit (bit 7) of the Command Register.
When
CRPS
is logic 0, this pin is an input pin and overrides the CBC/
ECB
bit of the Command
Register.
CBC/
ECB
2
2
42
I/O
CLK
CRPS
9
20
9
20
9
25
I
I
Clock:
System clock input.
Command Register Pin Select:
This input selects DAL bus or input pin programming of the
Command Register.
CRPS
high or open selects DAL bus programming.
CRPS
low selects input
pin programming.This input incorporates an internal pull-up resistor.
Chip Select:
CS
CS
10
11-18
10
11-18
10
11,12,15,
16,18,19,2
1,23
I
I/O
is made low to access registers within the device.
DAL 7 - 0
Data Lines:
Eight active true, tri-state, bi-directional I/O lines used for information transfer to
and from the DES device. All
Command Register, Status Register, Key Word
and
Data Word
transfers are via this bus.
Data-In Request:
This output is active high when the DES device is requesting that byte of the
Data Word
be written into the Data Register (The Data Register is automatically addressed when
DIR is active, unless overridden by A0).
Data-Out Request:
This output is active high when the DES device is requesting that a byte of
the
Data Word
be read from the Data Register (The Data Register is automatically addressed
when the DOR is active, unless overridden by A0).
Encrypt/Decrypt:
When
CRPS
is high or open, this pin is an output reflecting the status of the
Encrypt/Decrypt
bit (bit 3) of the Command Register.
When
CRPS
is low, this pin is an input pin that overrides the
Encrypt/Decrypt
bit of the
Command Register.
DIR
27
27
36
O
DOR
28
28
37
O
E
/D
24
24
31
I/O
3-4
Tundra Semiconductor Corporation
Tundra Semiconductor Corporation
Table 3-2 : Pin Description
Cont'd
Pin
Symbol
PLCC
IVIR
3
CA20C03A
Type
PDIP
3
Name and Function
Initial Vector-In Request:
This output is active high when the device is requesting that a byte of
the
IV Word
be written into the IV register (The IV register is automatically addressed when
IVIR is active, unless overridden A0).
Key Parity Error:
This output is active low when enabled via the Command Register bit 2
(KEOE) and a parity error has been detected during loading of the Key Register.
Key Request:
This output is active high when the DES device is requesting that a byte of the
Key Word
be written into the Key Register. (The Key Register is automatically addressed when
KR is active, unless overridden by A0.)
Master Reset:
MR
active low resets the Command and Status Registers and resets internal
circuitry. (Requires active clock for reset operation.)
Read Enable:
The contents of the selected register are placed on the DAL bus lines when
and
RE
are made low.
CS
TQFP
43
O
KPE
22
22
28
O
KR
26
26
34
O
MR
21
21
26
I
RE
8
8
8
I
SPIR
4
4
44
O
Special Pattern-In:
This output is active high during battery back-up mode, when the device is
requesting that a byte of the
Special Pattern Word
be written into the Data Register (The Data
Register is automatically addressed when SPIR is active, unless overridden by A0).
Power Supply:
+5 V
±10%
Ground:
Ground
Write Enable:
Information on the DAL bus lines is written into the selected register when
and
WE
are made low.
CS
V
DD
V
SS
WE
5
25
7
5
25
7
1
33
7
-
-
I
Tundra Semiconductor Corporation
3-5
FPGA/CPLD
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