PIP201-12M-3
DC-to-DC converter powertrain
M3D797
Rev. 03 — 19 November 2003
Product data
1. Description
The PIP201-12M is designed for use as the power output stage of a synchronous
buck DC-to-DC converter. It contains a MOSFET control IC and two power MOSFET
transistors. By combining the power MOSFETs and the driver circuit into a single
component, stray inductances are virtually eliminated, resulting in higher switching
frequency, lower switching losses and a compact, efficient design.
2. Features
s
s
s
s
s
s
s
Input conversion range from 3.3 V to 12 V
Output voltages from 0.8 V to 5 V
Capable of up to 20 A continuous output current
Operating frequency up to 1 MHz
Peak system efficiency >90% at 500 kHz
Low-profile, surface mount package (10
×
10
×
0.85 mm)
Compatible with any single or multi-phase PWM controller.
3. Applications
s
High-current DC-to-DC point-of-load converters
s
Small form-factor Voltage Regulator Modules
s
Microprocessor and memory voltage regulators.
4. Ordering information
Table 1:
Ordering information
Package
Name
PIP201-12M-3
HVQFN68
(MLF68)
Description
Version
plastic thermal enhanced very thin quad flat package; no leads; SOT687-1
68 terminals; body 10
×
10
×
0.85 mm
Type number
Philips Semiconductors
PIP201-12M-3
DC-to-DC converter powertrain
5. Block diagram
VDDC
CB
11, 12
bootstrap
capacitor
driveH
sourceH
10, 26, 27,
45 to 59
62 to 67, PAD3
VDDO
1 to 8, 60, 61
68, PAD1
PIP201-12M
13, 14
control cct
supply
VI
16, 17
PWM
input
VO
VSSC
n.c.
9, 15
22 to 24, PAD2 control
cct gnd
18 to 21, 25
driveL
sourceL
28 to 44
VSSO
03ae80
A bootstrap diode is integrated into the design of the PIP201-12M between V
DDC
and CB.
Fig 1. Block diagram.
6. Pinning information
6.1 Pinning
VDDO
VO
VO
VO
VO
VO
VO
VDDO
VDDO
VO
VO
VO
VO
VO
VO
VO
VO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VSSC
VO
CB
CB
VDDC
VDDC
VSSC
VI
VI
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
VDDO
PAD 1
VO
PAD 3
VSSC
PAD 2
PIP201-12M
VSSC
VSSC
VSSC
n.c.
VO
VO
VSSO
VSSO
VSSO
VSSO
VSSO
VSSO
VSSO
n.c.
n.c.
n.c.
n.c.
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
VO
VO
VO
VO
VO
VO
VO
VSSO
VSSO
V SSO
VSSO
VSSO
VSSO
VSSO
VSSO
VSSO
VSSO
03ae83
Shaded area denotes terminal 1 index area.
Fig 2. Pin configuration (footprint view).
9397 750 11942
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 03 — 19 November 2003
2 of 20
Philips Semiconductors
PIP201-12M-3
DC-to-DC converter powertrain
6.2 Pin description
Table 2:
Symbol
V
DDO
V
SSC
V
O
Pin description
Pin
1 to 8, 60, 61,
68
9, 15, 22 to 24
10, 26, 27,
45 to 59,
62 to 67
11, 12
13, 14
16, 17
28 to 44
18 to 21, 25
[5]
[1] [4]
I/O
-
-
O
Description
output stage supply voltage
control circuit supply ground
output
[2] [4]
[3] [4]
CB
V
DDC
VI
V
SSO
n.c.
[1]
[2]
[3]
[4]
[5]
I/O
-
I
-
-
bootstrap capacitor connection
control circuit supply voltage
pulse width modulated input
output stage supply ground
no internal connection
All pins connected to PAD1
All pins connected to PAD2
All pins connected to PAD3.
PAD1, PAD2 and PAD3 are electrical connections and must be soldered to the printed circuit board.
All n.c. pins should be connected to V
SSC
.
7. Functional description
7.1 Basic functionality
output stage supply voltage
control circuit supply (12 V)
100
nF
VDDO
VO
VSSO
Lout
output
Cout
VDDC CB
input voltage
VI
from PWM controller
VI
tp
T
δ
=
tp
T
VSSC
signal ground power ground
03ad36
Fig 3. Simplified functional block diagram of a synchronous DC-to-DC converter
output stage.
In order to understand the functions performed by the PIP201-12M, consider the
requirements of a synchronous DC-to-DC converter output stage, driven from a PWM
controller (Figure
3).
When the input voltage is HIGH, the upper MOSFET must be on and the lower
MOSFET must be off. Current flows from the supply (V
DDO
), through the upper
MOSFET and the inductor (L
out
), to the output.
9397 750 11942
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 03 — 19 November 2003
3 of 20
Philips Semiconductors
PIP201-12M-3
DC-to-DC converter powertrain
When the input voltage is LOW and current is flowing in the inductor, the upper
MOSFET must be off and the lower MOSFET must be on. Current flows from the
power ground (V
SSO
), through the lower MOSFET and the inductor (L
out
), to the
output.
Finally, when switching between states, both MOSFETs must not be on at the same
time.
7.2 MOSFET driver function
input voltage
upper MOSFET
gate drive
delay
lower MOSFET
gate drive
delay
output voltage
03ag35
Fig 4. Input, output and gate drive waveforms of a synchronous DC-to-DC converter
output stage.
The input, output and gate drive waveforms are shown in
Figure 4.
When the input
voltage goes HIGH, the gate drive to the lower MOSFET immediately goes LOW. This
causes the output current to flow through the source-drain diode of the lower
MOSFET. This causes output voltage to fall from zero to approximately
−0.7
V.
After a delay, if the input voltage is still HIGH, the gate drive to the upper MOSFET
goes HIGH. This causes the output voltage to rise to the output stage supply voltage,
V
DDO.
When the input voltage goes LOW, the gate drive to the upper MOSFET immediately
goes LOW. The output voltage falls from V
DDO
, until it is clamped by the source-drain
diode of the synchronous FET at approximately
−0.7
V.
After a delay, if the input voltage is still LOW, the gate drive to the lower MOSFET
goes HIGH. The lower MOSFET turns on, and the output voltage rises from
−0.7
V to
zero.
7.3 Bootstrap diode
A bootstrap diode is integrated into the design of the PIP201-12M between V
DDC
and
CB.
9397 750 11942
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 03 — 19 November 2003
4 of 20
Philips Semiconductors
PIP201-12M-3
DC-to-DC converter powertrain
7.4 3-state function
If the input from the PWM controller becomes high impedance (3-state) for longer
than t
d(3-state)
, then both MOSFETs are turned off and the V
I
input is driven to 2.5 V by
an internal 2 x 10 kΩ resistor voltage divider between an internal 5 V reference and
ground. Once the V
I
input is outside the 3-state window for longer than t
d(3-state)
normal operation will commence.
8. Limiting values
Table 3: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DDC
V
DDO
V
I
V
O
V
CB
I
O(AV)
I
ORM
P
tot
T
stg
T
j
[1]
[2]
Parameter
control circuit supply voltage
output stage supply voltage
input voltage
output voltage
bootstrap voltage
average output current
repetitive peak output current
total power dissipation
storage temperature
junction temperature
Conditions
Min
−0.5
−0.5
−0.5
−0.5
−0.5
Max
15
25
5.25
V
O
+ 15
20
200
25
12
+150
+150
Unit
V
V
V
V
A
A
W
W
°C
°C
V
DDO
+ 0.5 V
V
DDC
= 12 V; T
pcb
≤
112
°C;
f
i
= 500 kHz;
Figure 5
V
DDC
= 12 V; t
p
≤
10
µs
T
pcb
= 25
°C
T
pcb
= 90
°C
[1]
[2]
[2]
-
-
-
-
−55
−55
Pulse width and repetition rate limited by maximum value of T
j
.
Assumes a thermal resistance from junction to printed-circuit board of 5 K/W.
24
IO(AV)
(A)
20
03ae74
16
12
8
4
0
0
50
100
Tpcb (°C)
150
V
DDC
= 12 V; V
DDO
= 12 V; f
i
= 500 kHz; V
O
= 1.6 V.
Fig 5. Average output current as a function of printed-circuit board temperature.
9397 750 11942
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 03 — 19 November 2003
5 of 20
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