Intel StrataFlash
®
Cellular Memory (M18)
Datasheet
Product Features
■
High Performance Read, Program and Erase
— 96 ns initial access for reads
— 512-Mbit device: 108 MHz with zero wait-state
synchronous burst reads: 7 ns clock-to-data
output
— 256-Mbit device: 133 MHz with zero wait-state
synchronous burst reads: 5.5 ns clock-to-data
output
— 8-, 16-, and continuous-word synchronous-
burst
— Programmable WAIT configuration
— Customer-configurable output driver
impedance
— Buffered Enhanced Factory Programming
(BEFP): 2.1
μs/byte
(typ)
— 1.8 V low-power buffered programming:
2.1
μs/byte
(typ)
— Block Erase: 0.9 s per block (typ)
■
Power
— Core voltage: 1.7 V - 2.0 V
— I/O voltage: 1.7 V - 2.0 V
— Standby current: 50
μA
(typ)
— Deep Power-Down mode: 2
μA
(typ)
— Automatic Power Savings mode
— 16-word synchronous-burst read current: 23
mA (typ)
■
Software
— 20
μs
(typ) program suspend
— 20
μs
(typ) erase suspend
— Intel® Flash Data Integrator optimized
— Basic Command Set (BCS) and Extended
Command Set (ECS) compatible
— Common Flash Interface (CFI)
■
Security
— OTP Registers:
— 64 unique pre-programmed bits
— 64 user-programmable bits
— Additional 2048 user-programmable bits
— Absolute write protection with V
PP
= GND
— Power-transition erase/program lockout
— Individual zero-latency block locking
— Individual block lock-down
■
Architecture
— 16-bit wide data bus
— Multi-Level Cell Technology
— Symmetrically Blocked Array Architecture
— 256-Kbyte Erase Blocks
— 512-Mb device: Eight 64-Mbit partitions
— 256-Mb device: Eight 32-Mbit partitions
— Four additional 8-Kbyte Extended Flash Array
(EFA) Blocks
— Read-While-Program and Read-While-Erase
— Status register for partition and device status
— Blank Check feature
■
Density and Packaging
— Density: 512 Mbit, 256 Mbit
— Address-data multiplexed and non-multiplexed
— x16D (105-ball) Flash SCSP package
— x16C (107-ball) Flash SCSP package
— 0.8 mm solder-ball pitch lead-free
■
Quality and Reliability
— Expanded temperature: –30° C to +85° C
— Minimum 100,000 erase cycles per block
— ETOX™ IX Process Technology (90 nm)
The Intel StrataFlash
®
Cellular Memory (M18) is the 5
th
generation Intel StrataFlash
®
memory
with multi-level cell (MLC) technology. It provides high performance, low-power synchronous-
burst read mode and asynchronous read mode at 1.8 V. It features flexible, multi-partition read-
while-program and read-while-erase capability, enabling background programming or erasing in
one partition simultaneously with code execution or data reads in another partition. This dual
operation architecture also allows two processors to interleave code operations while program
and erase operations take place in the background. The eight partitions allow flexibility for
system designers to choose the size of the code and data segments. The Intel StrataFlash
®
Cellular Memory (M18) is manufactured using Intel 90 nm ETOX™ IX process technology and
is available in industry-standard chip-scale packaging.
Order Number: 309823, Revision: 003
23-Feb-2006
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
This document contains information on products in the design phase of development. The information here is subject to change without notice. Do not
finalize a design with this information.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at
http://www.intel.com.
Copyright © 2006, Intel Corporation
* Other names and brands may be claimed as the property of others.
23-Feb-2006
2
Intel StrataFlash
®
Cellular Memory (M18)
Order Number: 309823, Revision: 003
Datasheet
Intel StrataFlash
®
Cellular Memory
Contents
1.0
Introduction....................................................................................................................................7
1.1
1.2
1.3
1.4
2.0
2.1
2.2
3.0
4.0
Document Purpose ............................................................................................................. 7
Nomenclature .....................................................................................................................7
Acronyms............................................................................................................................7
Conventions........................................................................................................................8
Product Description ............................................................................................................ 9
Configuration and Memory Map ......................................................................................... 9
2.2.1 Extended Flash Array .......................................................................................... 11
Functional Overview
.....................................................................................................................9
Package Information
...................................................................................................................13
Ballout and Signal Descriptions
................................................................................................ 17
4.1
Signal Ballouts x16D ........................................................................................................17
4.1.1 x16D (105-Ball) Ballout, Non-Mux ....................................................................... 17
4.1.2 x16D AD-Mux (105-Ball) Ballout.......................................................................... 18
Signal Descriptions x16D ................................................................................................. 19
Signal Ballouts x16C ........................................................................................................23
4.3.1 x16C (107-Ball) Ballout, Non-Mux ....................................................................... 23
4.3.2 x16C AD-Mux (107-Ball) Ballout.......................................................................... 24
Signal Descriptions x16C ................................................................................................. 25
Absolute Maximum Ratings .............................................................................................. 29
Operating Conditions ........................................................................................................30
DC Current Specifications ................................................................................................ 31
DC Voltage Specifications ................................................................................................ 33
Capacitance......................................................................................................................33
AC Test Conditions........................................................................................................... 35
Read Specifications .......................................................................................................... 36
7.2.1 Timings: Non Mux Device, Asynchronous Read .................................................40
7.2.2 Timings: Non Mux Device, Synchronous Read 108 MHz, 512 Mb......................41
7.2.3 Timings: Non Mux Device, Synchronous Read 133 MHz, 256 Mb......................42
7.2.4 Timings: AD-Mux Device, Asynchronous Read................................................... 45
7.2.5 Timings: AD-Mux Device, Synchronous Read 108 MHz, 512 Mb ....................... 45
7.2.6 Timings: AD-Mux Device, Synchronous Read 133 MHz, 256 Mb ....................... 47
Write Specifications .......................................................................................................... 49
7.3.1 Timings: Non Mux Device, Asynchronous Write.................................................. 50
7.3.2 Timings: Non Mux Device, Synchronous Write 108 MHz, 512 Mb ......................52
7.3.3 Timings: Non Mux Device, Synchronous Write 133 MHz, 256 Mb ......................54
7.3.4 Timings: AD-Mux Device, Asynchronous Write ................................................... 55
7.3.5 Timings: AD-Mux Device, Synchronous Write 108 MHz, 512 Mb ....................... 56
4.2
4.3
4.4
5.0
5.1
5.2
6.0
6.1
6.2
6.3
7.0
7.1
7.2
Maximum Ratings and Operating Conditions...........................................................................29
Electrical Characteristics............................................................................................................31
NOR Flash AC Characteristics
...................................................................................................34
7.3
Datasheet
Intel StrataFlash
®
Cellular Memory (M18)
Order Number: 309823, Revision: 003
23-Feb-2006
3
Intel StrataFlash
®
Cellular Memory
7.4
7.5
7.6
8.0
8.1
7.3.6 Timings: AD-Mux Device, Synchronous Write 133 MHz, 256 Mb ....................... 57
Program and Erase Characteristics.................................................................................. 59
Reset Specifications ......................................................................................................... 60
Deep Power Down Specifications .................................................................................... 61
Bus Reads ........................................................................................................................ 62
8.1.1 Asynchronous single-word reads ........................................................................ 63
8.1.2 Asynchronous Page Mode (Non-multiplexed devices only) ................................ 63
8.1.3 Synchronous Burst Mode .................................................................................... 63
8.1.3.1 WAIT Operation ................................................................................... 64
Bus Writes ........................................................................................................................ 64
Reset ................................................................................................................................ 64
Deep Power-Down .......................................................................................................... 64
Standby ............................................................................................................................ 65
Output Disable.................................................................................................................. 65
Bus Cycle Interleaving...................................................................................................... 65
8.7.1 Read Operation During Program Buffer fill.......................................................... 66
Read-to-Write and Write-to-Read Bus Transitions ........................................................... 66
8.8.1 Write to Asynchronous read transition................................................................. 66
8.8.2 Write to synchronous read transition ................................................................... 66
8.8.3 Asynchronous/Synchronous read to write transition ........................................... 67
8.8.4 Bus write with active clock................................................................................... 67
Initialization....................................................................................................................... 68
9.1.1 Power-Up/Down Characteristics.......................................................................... 68
9.1.2 Reset Characteristics .......................................................................................... 68
9.1.3 Power Supply Decoupling ................................................................................... 69
Status Register ................................................................................................................. 69
9.2.1 Clearing the Status Register................................................................................ 70
Read Configuration Register ............................................................................................ 71
9.3.1 Latency Count ..................................................................................................... 72
9.3.2 Programming the RCR ........................................................................................ 73
Enhanced Configuration Register .................................................................................... 74
9.4.1 Output Driver Control .......................................................................................... 75
9.4.2 Programming the ECR ....................................................................................... 75
Read Operations .............................................................................................................. 76
9.5.1 Read Array .......................................................................................................... 76
9.5.2 Read Status Register .......................................................................................... 77
9.5.3 Read Device Information ..................................................................................... 77
9.5.4 CFI Query ............................................................................................................ 78
9.5.5 Read Extended Flash Array (EFA) ..................................................................... 78
Programming Modes ........................................................................................................ 78
9.6.1 Control Mode ....................................................................................................... 79
9.6.2 Object Mode ........................................................................................................ 80
Programming Operations ................................................................................................. 82
9.7.1 Single-Word Programming .................................................................................. 82
9.7.2 Buffered Programming ........................................................................................ 83
9.7.3 Buffered Enhanced Factory Programming (BEFP) ............................................ 84
NOR Flash Bus Interface
............................................................................................................ 62
8.2
8.3
8.4
8.5
8.6
8.7
8.8
9.0
NOR Flash Operations
................................................................................................................ 68
9.1
9.2
9.3
9.4
9.5
9.6
9.7
23-Feb-2006
4
Intel StrataFlash
®
Cellular Memory (M18)
Order Number: 309823, Revision: 003
Datasheet
Intel StrataFlash
®
Cellular Memory
9.8
9.9
9.10
9.11
9.12
9.7.3.1 Setup Phase ........................................................................................85
9.7.3.2 Program/Verify Phase.......................................................................... 85
9.7.3.3 Exit Phase............................................................................................85
9.7.4 EFA Word Programming .....................................................................................86
Block Erase Operations .................................................................................................... 86
Blank Check Operation .................................................................................................... 87
Suspend and Resume ......................................................................................................88
Simultaneous Operations ................................................................................................. 90
Security.............................................................................................................................91
9.12.1 Block Locking....................................................................................................... 91
9.12.2 One-Time Programmable (OTP) Registers ......................................................... 92
9.12.3 Global Main-Array Protection...............................................................................94
Device Command Codes..........................................................................................
95
Device ID Codes........................................................................................................
97
Flow Charts
............................................................................................................... 98
Common Flash Interface
........................................................................................ 107
Next State Table
...................................................................................................... 116
Additional Information............................................................................................
123
Ordering Information
.............................................................................................. 124
Appendix A
Appendix B
Appendix C
Appendix D
Appendix E
Appendix F
Appendix G
Datasheet
Intel StrataFlash
®
Cellular Memory (M18)
Order Number: 309823, Revision: 003
23-Feb-2006
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
