CAT524
Configured Digitally Programmable Potentiometer (DPP™): Programmable Voltage Applications
FEATURES
s
Four 8-bit DPPs configured as programmable
APPLICATIONS
s
Automated product calibration
s
Remote control adjustment of equipment
s
Offset, gain and zero adjustments in
voltage sources in DAC-like applications
s
Common reference inputs
s
Buffered wiper outputs
s
Non-volatile NVRAM memory wiper storage
s
Output voltage range includes both supply rails
s
4 independently addressable buffered
self-calibrating and adaptive control systems
s
Tamper-proof calibrations
s
DAC (with memory) substitute
output wipers
s
1 LSB accuracy, high resolution
s
Serial
µ
P interface
s
Single supply operation: 2.7V-5.5V
s
Setting read-back without effecting outputs
DESCRIPTION
The CAT524 is a quad, 8-bit digitally-programmable
potentiometer (DPP™) configured for programmable
voltage and DAC-like applications. Intended for final
calibration of products such as camcorders, fax
machines and cellular telephones on automated high
volume production lines, it is also well suited for
self-calibrating systems and for applications where
equipment which requires periodic adjustment is either
difficult to access or in a hazardous environment.
The four independently programmable DPPs have an
output range which includes both supply rails. The
wipers are buffered by rail to rail op amps. Wiper
settings, stored in non-volatile NVRAM memory, are not
lost when the device is powered down and are automati-
cally reinstated when power is returned. Each wiper can
be dithered to test new output values without effecting
FUNCTIONAL DIAGRAM
RDY/BSY
V
DD
1
V
H
REF
14
3
the stored settings, and stored settings can be read back
without disturbing the DPP’s output.
The CAT524 is controlled with a simple 3 wire serial
interface. A Chip Select pin allows several devices to
share a common serial interface. Communication back
to the host controller is via a single serial data line thanks
to the Tri-Stated CAT524 Data Output pin. A RDY/BSY
output working in concert with an internal low voltage
detector signals proper operation of the non-volatile
NVRAM memory Erase/Write cycle.
The CAT524 is available in the 0 to 70° C commercial
and –40° C to 85° C industrial operating temperature
ranges. Both 14-pin plastic DIP and SOIC packages are
offered.
PIN CONFIGURATION
DIP Package (P)
SOIC Package (J)
VDD
CLK
RDY/BSY
CS
DI
DO
PROG
1
2
3
14
13
VREFH
VOUT1
VOUT 2
VOUT 3
VOUT 4
VREF L
GND
PROG
7
PROGRAM
CONTROL
+
–
13
V
1
OUT
VDD
CLK
RDY/BSY
CS
DI
DO
PROG
1
2
3
14
13
12
VREFH
VOUT1
VOUT2
VOUT3
VOUT 4
VREF L
GND
DI
5
+
–
12
VOUT2
CLK
2
SERIAL
CONTROL
NVRAM
+
11
CAT
4
11
524
5
10
12
CAT
11
4
524
5
10
6
7
9
8
CS
4
–
V
3
OUT
6
7
9
8
+
–
10
VOUT4
SERIAL
DATA
OUTPUT
REGISTER
6
DO
CAT524
8
GND
9
V
L
REF
© 2001 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25076-00 4/01 M-1
CAT524
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage
V
DD
to GND ...................................... –0.5V to +7V
Inputs
CLK to GND ............................ –0.5V to V
DD
+0.5V
CS to GND .............................. –0.5V to V
DD
+0.5V
DI to GND ............................... –0.5V to V
DD
+0.5V
PROG to GND ........................ –0.5V to V
DD
+0.5V
V
REF
H to GND ........................ –0.5V to V
DD
+0.5V
V
REF
L to GND ......................... –0.5V to V
DD
+0.5V
Outputs
D
0
to GND ............................... –0.5V to V
DD
+0.5V
V
OUT
1– 4 to GND ................... –0.5V to V
DD
+0.5V
Operating Ambient Temperature
Commercial (‘C’ or Blank suffix) ...... 0°C to +70°C
Industrial (‘I’ suffix) ...................... – 40°C to +85°C
RELIABILITY CHARACTERISTICS
Symbol
V
ZAP(1)
I
LTH(1)(2)
Junction Temperature ..................................... +150°C
Storage Temperature ....................... –65°C to +150°C
Lead Soldering (10 sec max) .......................... +300°C
* Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Absolute
Maximum Ratings are limited values applied individually while
other parameters are within specified operating conditions,
and functional operation at any of these conditions is NOT
implied. Device performance and reliability may be impaired by
exposure to absolute rating conditions for extended periods of
time.
Parameter
ESD Susceptibility
Latch-Up
Min
2000
100
Max
Units
Volts
mA
Test Method
MIL-STD-883, Test Method 3015
JEDEC Standard 17
NOTES:
1. This parameter is tested initially and after a design or process change that affects the parameter.
2. Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to V
CC
+ 1V.
DC ELECTRICAL CHARACTERISTICS:
V
DD
= +2.7 to +5.5V, V
REF
H = V
DD
, V
REF
L = 0V, unless otherwise specified
Symbol
Accuracy
INL
Integral Linearity Error
I
LOAD
= 10
µA
I
LOAD
= 10
µA
I
LOAD
= 40
µA
I
LOAD
= 40
µA
I
LOAD
= 10
µA
I
LOAD
= 10
µA
I
LOAD
= 40
µA
I
LOAD
= 40
µA
T
R
= C
T
R
= I
T
R
= C
T
R
= I
T
R
= C
T
R
= I
T
R
= C
T
R
= I
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
±
1
±
1
±
2
±
2
±
0.5
±
0.5
±
1.5
±
1.5
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
Parameter
Resolution
Conditions
Min
8
Typ
—
Max
—
Units
Bits
DNL
Differential Linearity Error
Logic Inputs
I
IH
I
IL
V
IH
V
IL
Input Leakage Current
Input Leakage Current
High Level Input Voltage
Low Level Input Voltage
V
REF
H Input Voltage Range
V
REF
L Input Voltage Range
V
REF
H–V
REF
L Resistance
High Level Output Voltage
Low Level Output Voltage
I
OH
= – 40
µA
I
OL
= 1 mA, V
DD
= +5V
I
OL
= 0.4 mA, V
DD
= +3V
Doc. No. 25076-00 Rev. 4/01 M-1
V
IN
= V
DD
V
IN
= 0V
—
—
2
0
2.7
GND
—
V
DD
–0.3
—
—
—
—
—
—
—
—
7
—
—
—
10
–10
V
DD
0.8
V
DD
V
DD
-2.7
—
—
0.4
0.4
µA
µA
V
V
V
V
kΩ
V
V
V
References
V
RH
V
RL
Z
IN
V
OH
V
OL
Logic Outputs
2
CAT524
DC ELECTRICAL CHARACTERISTICS
(Cont.):
V
DD
= +2.7V to +5.5V , V
REF
H = +V
DD
, V
REF
L = 0V, unless otherwise specified
Symbol
FSO
ZSO
I
L
R
OUT
PSSR
TC
O
TC
REF
Parameter
Full-Scale Output Voltage
Zero-Scale Output Voltage
DAC Output Load Current
DAC Output Impedance
Power Supply Rejection
V
OUT
Temperature Coefficient
Temperature Coefficient of
V
REF
Resistance
Supply Current (Read)
Supply Current (Write)
Operating Voltage Range
Conditions
V
R
= V
REF
H–V
REF
L
V
R
= V
REF
H–V
REF
L
V
DD
= +5V
V
DD
= +3V
I
LOAD
= 250 nA
V
REF
H = +5V, V
REF
L = 0V
V
DD
= +5V, I
LOAD
= 250nA
V
REF
H to V
REF
L
Min
0.99 V
R
—
—
—
—
—
—
—
Typ
0.995 V
R
0.005 V
R
—
—
—
—
—
700
Max
—
0.01 V
R
1
100
150
1
200
—
Units
V
V
µA
kΩ
kΩ
LSB / V
µV/ °C
ppm /
°C
Analog Output
Temperature
Power Supply
I
DD1
I
DD2
V
DD
Normal Operating
V
DD
=5V
V
DD
=3V
—
—
—
2.7
400
1600
1000
—
600
2500
1600
5.5
µA
µA
µA
V
AC ELECTRICAL CHARACTERISTICS:
V
DD
= +2.7V to +5.5V, V
REF
H = +V
DD
, V
REF
L = 0V, unless otherwise specified
Symbol
Digital
t
CSMIN
t
CSS
t
CSH
t
DIS
t
DIH
t
DO1
t
DO0
t
HZ
t
Busy
t
LZ
t
PROG
t
PS
t
CLK
H
t
CLK
L
f
C
Minimum CS Low Time
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
Output Delay to 1
Output Delay to 0
Output Delay to High-Z
Erase/Write Cycle Time
Output Delay to Low-Z
Erase/Write Pulse Width
PROG Setup Time
Minimum CLK High Time
Minimum CLK Low Time
Clock Frequency
DAC Settling Time to 1/2 LSB
150
100
0
50
50
—
—
—
—
—
700
150
500
300
DC
—
—
—
—
—
—
—
—
—
—
—
400
4
400
—
—
—
—
—
3
6
8
6
—
—
—
—
—
150
150
—
5
—
—
—
—
—
1
10
10
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
MHz
µs
µs
pF
pF
Parameter
Conditions
Min
Typ
Max
Units
C
L
= 100 pF,
see note 1
Analog
t
DS
C
LOAD
= 10 pF, V
DD
= +5V
C
LOAD
= 10 pF, V
DD
= +3V
V
IN
= 0V, f = 1 MHz
(2)
V
OUT
= 0V, f = 1 MHz
(2)
Pin Capacitance
C
IN
C
OUT
Input Capacitance
Output Capacitance
NOTES:
1. All timing measurements are defined at the point of signal crossing V
DD
/ 2.
2. These parameters are periodically sampled and are not 100% tested.
3
Doc. No. 25076-00 Rev. 4/01
TIMING
MIN/MAX
FROM
TO
CAT524
to
2
3
4
5
1
PARAM
NAME
t CLK H
t CLK H
Rising CLK edge to falling CLK edge
Min
A. C. TIMING DIAGRAM
Doc. No. 25076-00 Rev. 4/01 M-1
CLK
t CLK L
Falling CLK edge to CLK rising edge
t CSH
t CLK L
t CSS
t CSH
Falling CLK edge for last data bit (DI)
to falling CS edge
Rising CS edge to next rising CLK edge
Min
Min
t CSS
Min
CS
t CSMIN
t CSMIN
Falling CS edge to rising CS edge
t DIS
Data valid to first rising CLK
edge after CS = high
Min
Min
t DIS
DI
t DIH
t DO0
t LZ
t DO0
Rising CLK edge to end of data valid
Min
4
t HZ
t DO1
t HZ
t PS
t PS
t PROG
t BUSY
3
4
5
t DIH
Rising CLK edge to D0 = low
Rising CS edge to D0 becoming high
low impedance (active output)
Max
(Max)
t LZ
DO
Rising CLK edge to D0 = high
Falling CS edge to D0 becoming high
impedance (Tri-State)
Max
(Max)
t DO1
PROG
Rising PROG edge to next rising
CLK edge
t PROG
Rising PROG edge to falling
PROG edge
t BUSY
Falling CLK edge after PROG=H to
rising RDY/BSY edge
Min
Min
RDY/BSY
Max
to
1
2
CAT524
PIN DESCRIPTION
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DAC addressing is as follows:
Function
Power supply positive.
Clock input pin.Clock input pin.
Ready/Busy Output
Chip Select
Serial data input pin.
Serial data output pin.
EEPROM Programming Enable
Input
Power supply ground.
Minimum DAC output voltage.
DAC output channel 4.
DAC output channel 3.
DAC output channel 2.
DAC output channel 1.
Maximum DAC output voltage.
Name
V
DD
CLK
RDY/BSY
CS
DI
DO
PROG
GND
V
REF
L
V
OUT
4
V
OUT
3
V
OUT
2
V
OUT
1
V
REF
H
DAC OUTPUT
V
OUT
1
V
OUT
2
V
OUT
3
V
OUT
4
A0
0
1
0
1
A1
0
0
1
1
DEVICE OPERATION
The CAT524 is a quad 8-bit Digital to Analog Converter
(DAC) whose outputs can be programmed to any one of
256 individual voltage steps. Once programmed, these
output settings are retained in non-volatile EEPROM
memory and will not be lost when power is removed from
the chip. Upon power up the DACs return to the settings
stored in EEPROM memory. Each DAC can be written
to and read from independently without effecting the
output voltage during the read or write cycle. Each
output can also be temporarily adjusted without chang-
ing the stored output setting, which is useful for testing
new output settings before storing them in memory.
DIGITAL INTERFACE
The CAT524 employs a standard 3 wire serial control
interface consisting of Clock (CLK), Chip Select (CS)
and Data In (DI) inputs. For all operations, address and
data are shifted in LSB first. In addition, all digital data
must be preceded by a logic “1” as a start bit. The DAC
address and data are clocked into the DI pin on the
clock’s rising edge. When sending multiple blocks of
information a minimum of two clock cycles is required
between the last block sent and the next start bit.
Multiple devices may share a common input data line by
selectively activating the CS control of the desired IC.
Data Outputs (DO) can also share a common line
because the DO pin is Tri-Stated and returns to a high
impedance when not in use.
CHIP SELECT
Chip Select (CS) enables and disables the CAT524’s
read and write operations. When CS is high data may be
read to or from the chip, and the Data Output (DO) pin is
active. Data loaded into the DAC control registers will
remain in effect until CS goes low. Bringing CS to a logic
low returns all DAC outputs to the settings stored in
EEPROM memory and switches DO to its high imped-
ance Tri-State mode.
Because CS functions like a reset the CS pin has been
equipped with a 30 ns to 90 ns filter circuit to prevent
noise spikes from causing unwanted resets and the loss
of volatile data.
CLOCK
The CAT524’s clock controls both data flow in and out of
the IC and EEPROM memory cell programming. Serial
data is shifted into the DI pin and out of the DO pin on the
clock’s rising edge. While it is not necessary for the clock
to be running between data transfers, the clock must be
operating in order to write to EEPROM memory, even
though the data being saved may already be resident in
the DAC control register.
No clock is necessary upon system power-up. The
CAT524’s internal power-on reset circuitry loads data
from EEPROM to the DACs without using the external
clock.
As data transfers are edge triggered clean clock transi-
tions are necessary to avoid falsely clocking data into the
control registers. Standard CMOS and TTL logic fami-
lies work well in this regard and it is recommended that
any mechanical switches used for breadboarding or
device evaluation purposes be debounced by a flip-flop
or other suitable debouncing circuit.
5
Doc. No. 25076-00 Rev. 4/01
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
