CAT515
8-Bit Quad Digital POT with Independent Reference Inputs
FEATURES
s
Output settings retained without power
s
Independent Reference Inputs
s
Output range includes both supply rails
s
Programming voltage generated on-chip
s
4 independently addressable outputs
s
Serial
µ
P interface
s
Single supply operation: 2.7V-5.5V
APPLICATIONS
s
Automated product calibration.
s
Remote control adjustment of equipment
s
Offset, gain and zero adjustments in Self-
Calibrating and Adaptive Control systems.
s
Tamper-proof calibrations.
DESCRIPTION
The CAT515 is a quad 8-Bit Memory DAC designed as
an electronic replacement for mechanical potentiom-
eters and trim pots. Intended for final calibration of
products such as camcorders, fax machines and cellular
telephones on automated high volume production lines
and systems capable of self calibration, it is also well
suited for applications were equipment requiring peri-
odic adjustment is either difficult to access or located in
a hazardous environment.
The CAT515 offers 4 independently programmable DACs
each having its own reference inputs and each capable
of rail to rail output swing. Output settings, stored non-
volatile EEPROM memory, are not lost when the device
is powered down and are automatically reinstated when
power is returned. Each output can be dithered to test
new output values without effecting the stored settings
and stored settings can be read back without disturbing
the DAC’s output.
FUNCTIONAL DIAGRAM
RDY/BSY
5
SERIAL DATA OUTPUT
VDD
Control of the CAT515 is accomplished with a simple 3
wire serial interface. A Chip Select pin allows several
CAT515's to share a common serial interface and com-
munications back to the host controller is via a single
serial data line thanks to the CAT515’s Tri-Stated Data
Output pin. A RDY/BSYoutput working in concert with
an internal low voltage detector signals proper operation
of EEPROM Erase/Write cycle.
The CAT515 operates from a single 3–5 volt power
supply. The high voltage required for EEPROM Erase/
Write operations is generated on-chip.
The CAT515 is available in the 0°C to 70°C Commercial
and –40°C to +85°C Industrial operating temperature
ranges and offered in 20-pin plastic DIP and Surface
mount packages.
PIN CONFIGURATION
8
DO
3
DIP Package (P)
VREF H4
VREF H1
DVD
CLK
RDY/BSY
CS
DI
1
2
3
4
5
6
7
8
9
10
20
19
18
17
CAT515
SOIC Package (J)
1
2
3
4
5
6
7
8
9
10
CAT515
2
PROG
9
PROGRAM
CONTROL
EEPROM
LATCH
DAC 1
V REF H1
VOUT 1
V REF L1
VREF H2
VOUT 2
VREF L2
V REF H3
VOUT 3
V REF L3
V
REF
H4
VREF H3 VREF H4
VREF H4 V
H1
REF
VOUT1
DVD
VOUT2
V
3
OUT
VOUT4
VREF L4
VREF L3
VREF L2
VREF L1
CLK
RDY/BSY
CS
DI
DO
PROG
GND
20
19
18
17
16
15
14
13
12
11
VREF H3
VREF H4
VOUT1
VOUT2
V
3
OUT
VOUT4
VREF L4
VREF L3
VREF L2
VREF L1
18
11
1
CLK
4
DATA
CONTROLLER
EEPROM
LATCH
DAC 2
17
12
20
CS
6
16
15
14
13
12
11
DI
7
EEPROM
LATCH
DAC 3
16
13
19
H.V.
CHARGE
PUMP
EEPROM
LATCH
DAC 4
DO
PROG
GND
15
14
VOUT 4
V REF L4
CAT515
10
GND
© 2000 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25077-00 2/98 M-1
CAT515
ABSOLUTE MAXIMUM RATINGS
Supply Voltage*
V
DD
to GND ...................................... –0.5V to +7V
Inputs
CLK to GND ............................ –0.5V to V
DD
+0.5V
CS to GND .............................. –0.5V to V
DD
+0.5V
DI to GND ............................... –0.5V to V
DD
+0.5V
RDY/BSY to GND ................... –0.5V to V
DD
+0.5V
PROG to GND ........................ –0.5V to V
DD
+0.5V
V
REF
H to GND ........................ –0.5V to V
DD
+0.5V
V
REF
L to GND ......................... –0.5V to V
DD
+0.5V
Outputs
D
0
to GND ............................... –0.5V to V
DD
+0.5V
V
OUT
1– 4 to GND ................... –0.5V to V
DD
+0.5V
Operating Ambient Temperature
Commercial (‘C’ suffix) .................... 0°C to +70°C
Industrial (‘I’ suffix) ...................... – 40°C to +85°C
Junction Temperature ..................................... +150°C
Storage Temperature ....................... –65°C to +150°C
Lead Soldering (10 sec max) .......................... +300°C
* Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Absolute
Maximum Ratings are limited values applied individually while
other parameters are within specified operating conditions,
and functional operation at any of these conditions is NOT
implied. Device performance and reliability may be impaired by
exposure to absolute rating conditions for extended periods of
time.
RELIABILITY CHARACTERISTICS
Symbol
V
ZAP(1)
I
LTH(1)(2)
Notes:
Parameter
ESD Susceptibility
Latch-Up
Min
2000
100
Max
Units
Volts
mA
Test Method
MIL-STD-883, Test Method 3015
JEDEC Standard 17
1. This parameter is tested initially and after a design or process change that affects the parameter.
2. Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to V
CC
+ 1V.
DC ELECTRICAL CHARACTERISTICS:
V
DD
= +2.7V to +5.5V, V
REF
H = V
DD
, V
REF
L = 0V, unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Resolution
8
I
LOAD
= 250 nA, T
R
= C
T
R
= I
I
LOAD
= 1
µA,
T
R
= C
T
R
= I
I
LOAD
= 250 nA, T
R
= C
T
R
= I
I
LOAD
= 1
µA,
T
R
= C
T
R
= I
V
IN
= V
DD
V
IN
= 0V
—
—
—
—
—
—
—
—
—
—
2
0
2.7
GND
—
—
I
OH
= – 40
µA
I
OL
= 1 mA, V
DD
= +5V
I
OL
= 0.4 mA, V
DD
= +3V
V
DD
–0.3
—
—
—
0.6
0.6
1.2
1.2
0.25
0.25
0.5
0.5
—
—
—
—
—
—
28K
±
0.5
—
—
—
—
±
1
±
1
—
—
±
0.5
±
0.5
—
—
10
–10
V
DD
0.8
V
DD
V
DD
-2.7
—
±
1
—
0.4
0.4
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
µA
µA
V
V
V
V
Ω
%
V
V
V
Accuracy
INL
Integral Linearity Error
DNL
Differential Linearity Error
Logic Inputs
I
IH
I
IL
V
IH
V
IL
Input Leakage Current
Input Leakage Current
High Level Input Voltage
Low Level Input Voltage
V
REF
H Input Voltage Range
V
REF
L Input Voltage Range
V
REF
H–V
REF
L Resistance
Input Resistance Match
High Level Output Voltage
Low Level Output Voltage
References
V
RH
V
RL
Z
IN
∆V
IN
/ R
IN
V
OH
V
OL
Logic Outputs
Doc. No. 25077-00 2/98 M-1
2
CAT515
DC ELECTRICAL CHARACTERISTICS
(Cont.):
V
DD
= +2.7V to +5.5V, V
REF
H = V
DD
, V
REF
L = 0V
, unless otherwise specified
Symbol
FSO
ZSO
I
L
R
OUT
PSSR
TC
O
TC
REF
Parameter
Full-Scale Output Voltage
Zero-Scale Output Voltage
DAC Output Load Current
DAC Output Impedance
Power Supply Rejection
V
OUT
Temperature Coefficient
Temperature Coefficient of
V
REF
Resistance
Supply Current (Read)
Supply Current (Write)
Operating Voltage Range
Conditions
V
R
= V
REF
H – V
REF
L
V
R
= V
REF
H – V
REF
L
V
DD
= V
REF
H = +5V
V
DD
= V
REF
H = +3V
I
LOAD
= 1
µA
V
DD
= +5V, I
LOAD
= 250nA
V
REF
H= +5V, V
REF
L = 0V
V
REF
H to V
REF
L
Min
0.99 V
R
—
—
—
—
—
—
—
Typ
0.995 V
R
0.005 V
R
—
—
—
—
—
700
Max
—
0.01 V
R
1
100K
150K
1
200
—
Units
V
V
µA
Ω
Ω
LSB / V
µV/ °C
ppm /
°C
Analog Output
Temperature
Power Supply
I
DD1
I
DD2
V
DD
Normal Operating
V
DD
= 5V
V
DD
= 3V
—
—
—
2.7
40
1200
600
—
50
2000
1200
5.5
µA
µA
µA
V
AC ELECTRICAL CHARACTERISTICS:
V
DD
= +2.7V to +5.5V, V
REF
H = V
DD
, V
REF
L = 0V
, unless otherwise specified
Symbol
Digital
t
CSMIN
t
CSS
t
CSH
t
DIS
t
DIH
t
DO1
t
DO0
t
HZ
t
LZ
t
BUSY
t
PS
t
PROG
t
CLK
H
t
CLK
L
f
C
Minimum CS Low Time
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
Output Delay to 1
Output Delay to 0
Output Delay to High-Z
Output Delay to Low-Z
Erase/Write Cycle Time
PROG Setup Time
Minimum Pulse Width
Minimum CLK High Time
Minimum CLK Low Time
Clock Frequency
DAC Settling Time to 1 LSB
150
100
0
50
50
—
—
—
—
—
150
700
500
300
DC
—
—
—
—
—
—
—
—
—
—
—
400
400
4
—
—
—
—
—
3
6
8
6
—
—
—
—
—
150
150
—
—
5
—
—
—
—
1
10
10
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
MHz
µs
µs
pF
pFNotes
Parameter
Conditions
Min
Typ
Max
Units
C
L
= 100 pF,
see note 1
Analog
t
DS
C
LOAD
= 10 pF, V
DD
= +5V
C
LOAD
= 10 pF, V
DD
= +3V
V
IN
= 0V, f = 1 MHz
(2)
V
OUT
= 0V, f = 1 MHz
2)
Pin Capacitance
C
IN
C
OUT
Input Capacitance
Output Capacitance
Notes: 1. All timing measurements are defined at the point of signal crossing V
DD
/ 2.
2. These parameters are periodically sampled and are not 100% tested.
3
Doc. No. 25077-00 2/98 M-1
CAT515
TIMING
MIN/MAX
FROM
TO
to
2
3
4
5
1
PARAM
NAME
A. C. TIMING DIAGRAM
Doc. No. 25077-00 2/98 M-1
t CLK H
t CLK H
Rising CLK edge to falling CLK edge
Min
CLK
t CLK L
Falling CLK edge to CLK rising edge
t CSH
t CLK L
t CSS
t CSH
Falling CLK edge for last data bit (DI)
to falling CS edge
Rising CS edge to next rising CLK edge
Min
Min
t CSS
Min
CS
t CSMIN
t CSMIN
Falling CS edge to rising CS edge
t DIS
Data valid to first rising CLK
edge after CS = high
Min
Min
t DIS
DI
t DIH
t DO0
t LZ
t DO0
Rising CLK edge to end of data valid
Min
4
t HZ
t DO1
t HZ
t PS
t PS
t PROG
t BUSY
3
4
5
t DIH
Rising CLK edge to D0 = low
Rising CS edge to D0 becoming high
low impedance (active output)
Max
(Max)
t LZ
DO
Rising CLK edge to D0 = high
Falling CS edge to D0 becoming high
impedance (Tri-State)
Max
(Max)
t DO1
PROG
Rising PROG edge to next rising
CLK edge
t PROG
Rising PROG edge to falling
PROG edge
t BUSY
Falling CLK edge after PROG=H to
rising RDY/BSY edge
Min
Min
RDY/BSY
Max
to
1
2
CAT515
PIN DESCRIPTION
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DAC addressing is as follows:
Function
Maximum DAC 2 output voltage
Maximum DAC 1 output voltage
Power supply positive
Clock input pin
Ready/Busy output
Chip select
Serial data input pin
Serial data output pin
EEPROM Programming Enable
Input
Power supply ground
Minimum DAC 1 output voltage
Minimum DAC 2 output voltage
Minimum DAC 3 output voltage
Minimum DAC 4 output voltage
DAC 4 output
DAC 3 output
DAC 2 output
DAC 1 output
Maximum DAC 4 output voltage
Maximum DAC 3 output voltage
Name
V
REF
H2
V
REF
H1
V
DD
CLK
RDY/BSY
CS
DI
DO
PROG
GND
V
REF
L1
V
REF
L2
V
REF
L3
V
REF
L4
V
OUT
4
V
OUT
3
V
OUT
2
V
OUT
1
V
REF
H4
V
REF
H3
DAC OUTPUT
V
OUT
1
V
OUT
2
V
OUT
3
V
OUT
4
A0
0
1
0
1
A1
0
0
1
1
DEVICE OPERATION
The CAT515 is a quad 8-bit Digital to Analog Converter
(DAC) whose outputs can be programmed to any one of
256 individual voltage steps. Once programmed, these
output settings are retained in non-volatile EEPROM
memory and will not be lost when power is removed from
the chip. Upon power up the DACs return to the settings
stored in EEPROM memory. Each DAC can be written
to and read from independently without effecting the
output voltage during the read or write cycle. Each
output can also be adjusted without altering the stored
output setting, which is useful for testing new output
settings before storing them in memory.
DIGITAL INTERFACE
The CAT515 employs a standard 3 wire serial control
interface consisting of Clock (CLK), Chip Select (CS)
and Data In (DI) inputs. For all operations, address and
data are shifted in LSB first. In addition, all digital data
must be preceded by a logic “1” as a start bit. The DAC
address and data are clocked into the DI pin on the
clock’s rising edge. When sending multiple blocks of
information a minimum of two clock cycles is required
between the last block sent and the next start bit.
Multiple devices may share a common input data line by
selectively activating the CS control of the desired IC.
Data Outputs (DO) can also share a common line
because the DO pin is Tri-Stated and returns to a high
impedance when not in use.
5
CHIP SELECT
Chip Select (CS) enables and disables the CAT515’s
read and write operations. When CS is high data may be
read to or from the chip, and the Data Output (DO) pin is
active. Data loaded into the DAC control registers will
remain in effect until CS goes low. Bringing CS to a logic
low returns all DAC outputs to the settings stored in
EEPROM memory and switches DO to its high imped-
ance Tri-State mode.
Because CS functions like a reset the CS pin has been
desensitized with a 30 ns to 90 ns filter circuit to prevent
noise spikes from causing unwanted resets and the loss
of volatile data.
CLOCK
The CAT515’s clock controls both data flow in and out of
the IC and EEPROM memory cell programming. Serial
data is shifted into the DI pin and out of the DO pin on the
clock’s rising edge. While it is not necessary for the clock
to be running between data transfers, the clock must be
operating in order to write to EEPROM memory, even
though the data being saved may already be resident in
the DAC control register.
No clock is necessary upon system power-up. The
CAT515’s internal power-on reset circuitry loads data
from EEPROM to the DACs without using the external
clock.
Doc. No. 25077-00 2/98 M-1
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