This 4-bit shift register is a monolithic complementary MOS
(CMOS) integrated circuit composed of four D flip-flops
This register will perform right-shift or left-shift operations
dependent upon the logical input level to the mode control
A number of these registers may be connected in series to
form an N-bit right-shift or left-shift register
When a logical ‘‘0’’ level is applied to the mode control in-
put the output of each flip-flop is coupled to the D input of
the succeeding flip flop Right-shift operation is performed
by clocking at the clock 1 input and serial data entered at
the serial input clock 2 and parallel inputs A through D are
inhibited With a logical ‘‘1’’ level applied to the mode con-
trol outputs to succeeding stages are decoupled and paral-
lel loading is possible or with external interconnection shift-
left operation can be accomplished by connecting the out-
put of each flip-flop to the parallel input of the previous
flip-flop and serial data is entered at input D
Features
Y
Medium speed operation
Y
Y
Y
Y
Y
Y
Y
Y
Applications
Y
Y
Y
Y
Block and Connection Diagrams
bs
ol
TL F 5890 – 1
Dual-In-Line Package
O
TL F 5890 – 4
Order Number MM54C95 or MM74C95
C
1995 National Semiconductor Corporation
TL F 5890
et
Y
Y
Y
Data terminals
Instrumentation
Automotive
Medical electronics
Mode Control
e
0 for Right Shift
Mode Control
e
1 for Left Shift or Parallel Load
e
Y
10 MHz (typ )
V
CC
e
10V C
L
e
50 pF
High noise immunity
0 45 V
CC
(typ )
Low power
100 nW (typ )
Tenth power TTL compatible
Drive 2 LTTL loads
Wide supply voltage range
3V to 15V
Synchronous parallel load
Parallel inputs and outputs from each flip-flop
Negative edge triggered clocking
The MM54C95 MM74C95 follows the MM54L95
MM74L95 Pinout
Alarm systems
Remote metering
Industrial electronics
Computers
TL F 5890 – 2
TL F 5890 – 3
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
b
0 3V to V
CC
a
0 3V
Voltage at any Pin
Operating Temperature Range (T
A
)
MM54C95
MM74C95
b
55 C to
a
125 C
b
40 C to
a
85 C
Storage Temperature (T
S
)
Maximum V
CC
Voltage
Power Dissipation (P
D
)
Dual-In-Line
Small Outline
Operating V
CC
Range
Lead Temperature (T
L
)
(Soldering 10 seconds)
b
65 C to
a
150 C
18V
700 mW
500 mW
a
3V to
a
15V
260 C
DC Electrical Characteristics
Min
Symbol
CMOS TO CMOS
V
IN(1)
V
IN(0)
V
OUT(1)
V
OUT(0)
I
IN(1)
I
IN(0)
I
CC
Logical ‘‘1’’ Input Voltage
Logical ‘‘0’’ Input Voltage
Logical ‘‘1’’ Output Voltage
Logical ‘‘0’’ Output Voltage
Logical ‘‘1’’ Input Current
Logical ‘‘0’’ Input Current
Supply Current
Parameter
Max limits apply across temperature range unless otherwise noted
Conditions
Min
Typ
Max
Units
V
CC
e
5V
V
CC
e
10V
V
CC
e
5V
V
CC
e
10V
V
CC
e
5V
V
CC
e
10V
V
CC
e
5V
V
CC
e
10V
V
CC
e
15V
V
CC
e
15V
V
CC
e
15V
35
80
15
20
45
90
V
V
V
V
V
V
V
V
LOW POWER TTL CMOS INTERFACE
V
IN(1)
V
IN(0)
V
OUT(1)
V
OUT(0)
Logical ‘‘1’’ Input Voltage
Logical ‘‘0’’ Input Voltage
bs
ol
54C V
CC
e
4 5V
74C V
CC
e
4 75V
54C V
CC
e
4 5V I
O
e
360
mA
74C V
CC
e
4 75V I
O
e
360
mA
54C V
CC
e
4 5V I
O
e
360
mA
74C V
CC
e
4 75V I
O
e
360
mA
24
24
V
CC
e
5V V
IN(0)
e
0V
T
A
e
25 C V
OUT
e
0V
b
1 75
b
8 0
54C V
CC
e
4 5V
74C V
CC
e
4 75V
et
10
b
1 0
Logical ‘‘1’’ Output Voltage
Logical ‘‘0’’ Output Voltage
OUTPUT DRIVE (See 54C 74C Family Characteristics Data Sheet)
I
SOURCE
I
SOURCE
I
SINK
I
SINK
Output Source Current
Output Source Current
Output Sink Current
Output Sink Current
V
CC
e
10V V
IN(0)
e
0V
T
A
e
25 C V
OUT
e
0V
O
V
CC
e
5V V
IN(1)
e
5V
T
A
e
25 C V
OUT
e
V
CC
V
CC
e
10V V
IN(1)
e
10V
T
A
e
25 C V
OUT
e
V
CC
Note 1
‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation
2
e
05
10
mA
mA
mA
0 050
300
V
CC
b
1 5
V
CC
b
1 5
V
V
V
V
V
V
04
04
V
V
08
08
mA
mA
mA
mA
1 75
80
AC Electrical Characteristics
Symbol
t
pd
t
S0
t
S1
t
H0
t
H1
t
PW
t
SM
f
MAX
C
IN
C
PD
Parameter
T
A
e
25 C C
L
e
50 pF unless otherwise noted
Conditions
V
CC
e
5V
V
CC
e
10V
V
CC
e
5V
V
CC
e
10V
V
CC
e
5V
V
CC
e
10V
V
CC
e
5V
V
CC
e
10V
V
CC
e
5V
V
CC
e
10V
V
CC
e
5V
V
CC
e
10V
Any Input (Note 2)
(Note 3)
200
100
3
65
60
25
25
10
Min
Typ
200
80
30
10
10
50
100
50
100
50
5
10
5
100
Max
400
160
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
pF
pF
Propagation Delay Time to a Logical
‘‘0’’ or Logical ‘‘1’’ from Clock to Q or Q
Time Prior to Clock Pulse that Data
must be Preset
Time After Clock Pulse that Data
must be Held
Minimum Clock Pulse Width (t
WL
e
t
WH
)
Time Prior to Clock Pulse that Mode
Control must be Preset
Maximum Input Clock Frequency
Input Capacitance
Power Dissipation Capacitance
AC Parameters are guaranteed by DC correlated testing
Note 1
‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation
Note 3
C
PD
determines the no load AC power consumption of any CMOS device For complete explanation see 54C 74C Family Characteristics Application Note
AN-90
Function Table
Inputs
Serial
X
X
X
X
H
L
X
X
X
X
X
X
X
bs
ol
Mode
Control
H
H
H
L
L
L
Clocks
Parallel
B
Q
A
Q
B
2 (L)
H
1 (R)
X
X
X
H
A
C
D
X
c
d
X
X
X
X
X
X
X
X
X
X
v
v
L
X
X
L
L
L
H
H
L
H
v
v
L
L
H
L
H
H
L
O
u
v
v
u
u
u
v
Shifting left requires external connection of Q
B
to A Q
C
to B and Q
D
to C Serial data is entered at input D
H
e
high level (steady state) L
e
low level (steady state) X
e
irrelevant (any input including transitions)
v
e
transition from high to low level
u
e
transition from low to high level
a b c d
e
the level of steady-state input at inputs A B C or D respectively
Q
A0
Q
B0
Q
C0
Q
D0
e
the level of Q
A
Q
B
Q
C
or Q
D
respectively before the indicated steady-state input conditions
were established
Q
An
Q
Bn
Q
Cn
Q
Dn
e
the level of Q
A
Q
B
Q
C
or Q
D
respectively before the most recent transition of the clock
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION As used herein
1 Life support devices or systems are devices or
systems which (a) are intended for surgical implant
into the body or (b) support or sustain life and whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling can
be reasonably expected to result in a significant injury
to the user
2 A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system or to affect its safety or
effectiveness
bs
ol
Molded Dual-In-Line Package (N)
Order Number MM54C95N or MM74C95N
NS Package Number N14A
National Semiconductor
Europe
Fax (
a
49) 0-180-530 85 86
Email cnjwge tevm2 nsc com
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a
49) 0-180-530 85 85
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a
49) 0-180-532 78 32
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a
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a
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National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications
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