FEMTOCLOCKS™ VCXO BASED WCDMA
CLOCK GENERATOR/JITTER ATTENUATOR
ICS843002I-72
G
ENERAL
D
ESCRIPTION
The ICS843002I-72 is a member of the
HiperClockS™ family of high performance clock
HiPerClockS™
solutions from IDT. The ICS843002I-72 is a
PLL based synchronous clock generator that is
optimized for WCDMA channel card applications
where jitter attenuation and frequency translation is needed.
The device contains two internal PLL stages that are cascaded
in series. The first PLL stage uses a VCXO which is optimized
to provide reference clock jitter attenuation and to be jitter
tolerant, and to provide a stable reference clock for the second
PLL stage. The second PLL stage provides additional frequency
multiplication (x32), and it maintains low output jitter by using a
low phase noise FemtoClock™ VCO. The device performance
and the PLL multiplication ratios are optimized to support
WCDMA applications. The VCXO requires the use of an
external, inexpensive pullable crystal. VCXO PLL uses external
passive loop filter components which are used to optimize the
PLL loop bandwidth and damping characteristics for the given
application.
F
EATURES
•
Two differential LVPECL outputs
•
CLK input accepts the following input levels:
LVCMOS or LVTTL levels
•
Output frequency: 122.88MHz (typical)
•
FemtoClock VCO frequency range: 490MHz - 680MHz
•
RMS phase jitter @ 122.88MHz, using a 19.2MHz crystal
(1.875MHz to 10MHz): 0.49ps (typical)
•
Deterministic jitter: 30fs (typical)
•
Random jitter, RMS: 2.2ps (typical)
•
Full 3.3V or mixed 3.3V core/2.5V output supply voltage
•
-40°C to 85°C ambient operating temperature
•
Available in lead-free (RoHS 6) package
IC
S
The ICS843002I-72 can accept a single-ended input. LOCK_DT
reports the lock status of VCXO PLL loop. If the reference clock
input is lost, it will set LOCK_DT to logic LOW.
Typical ICS843002I-72 configuration in WCDMA Systems:
•
19.2MHz pullable crystal
•
Input Reference clock frequency: 3.84MHz
•
Output clock frequency: 122.88MHz
P
IN
A
SSIGNMENT
XTAL_OUT
XTAL_IN
V
CC
V
CC
V
CC
V
EE
V
EE
nc
32 31 30 29 28 27 26 25
LF1
LF0
ISET
V
CC
V
CC
V
EE
V
EE
CLK
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
Q0
V
CCA
V
CCO
nOE
nQ0
V
EE
V
EE
V
EE
24
23
22
21
20
19
18
17
LOCK_DT
V
EE
V
CC
V
CCO
V
CCO
nQ1
Q1
V
EE
ICS843002I-72
32-Lead VFQFN
5mm x 5mm x 0.925 package body
K Package
Top View
IDT
™
/ ICS
™
WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
1
ICS843002BKI-72 REV. A NOVEMBER 21, 2007
ICS843002I-72
FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
B
LOCK
D
IAGRAM
122.88MHz
3.84MHz
CLK
Pulldown
FemtoClock
x32
Q0
nQ0
XTAL_IN
19.2MHz
Pullable Xtal
XTAL_OUT
VCXO
÷5
Phase
Detect
Charge
Pump
Pulldown
Q1
nQ1
External
Loop
Components
nOE
LF0
LF1
ISET
LF
LOCK_DT
NOTE 1: 19.2MHz pullable crystal shown is typical for WCDMA device applications.
IDT
™
/ ICS
™
WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
2
ICS843002BKI-72 REV. A NOVEMBER 21, 2007
ICS843002I-72
FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3
4, 5, 22, 28,
29, 30
6, 7, 9, 10, 13,
17, 23, 26, 27
8
11
12
14, 20, 21
15, 16
18, 19
24
Name
LF1, LF0
ISET
V
CC
V
EE
CL K
nOE
V
CCA
V
CCO
Q0, nQ0
Q1, nQ1
LOCK_DT
Type
Analog
Input/Output
Analog
Input/Output
Power
Power
Input
Input
Power
Power
Output
Output
Output
Description
Loop filter connection node pins.
Charge pump current setting pin.
Core power supply pins.
Negative supply pins.
Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.
Output enable pin. When LOW, output is enabled.
Pulldown
LVCMOS/LVTTL interface levels. See Table 3.
Analog supply pin.
Output power supply pin.
Differential clock output pair. LVPECL interface levels.
Differential clock output pair. LVPECL interface levels.
Lock detect. Logic HIGH when VCXO PLL loop is locked.
No connect.
Cr ystal oscillator interface. XTAL_OUT is the output.
XTAL_IN is the input.
2, Pin Characteristics, for typical values.
25
nc
Unused
31,
XTAL_OUT,
Input
32
XTAL_IN
NOTE:
Pulldown
refers to internal input resistors. See Table
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
Parameter
Input Capacitance
Input Pulldown Resistor
Test Conditions
Minimum Typical
4
50
Maximum
Units
pF
kΩ
T
ABLE
3. I
NPUT
R
EFERENCE
S
ELECTION
F
UNCTION
T
ABLE
Inputs
nOE
0
1
Outputs
Q0/nQ0, Q1/nQ1
Enabled
Hi-Z
IDT
™
/ ICS
™
WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
3
ICS843002BKI-72 REV. A NOVEMBER 21, 2007
ICS843002I-72
FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
(LVPECL)
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
37°C/W (0 mps)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCO
= 3.3V±5%, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
V
CC
– 0.13
3.135
Typical
3.3
3. 3
3.3
Maximum
3.465
V
CC
3.465
140
13
Units
V
V
V
mA
mA
T
ABLE
4B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, V
CCO
= 2.5V±5%, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
V
CC
– 0.13
2.375
Typical
3.3
3.3
2.5
Maximum
3.465
V
CC
2.625
140
13
Units
V
V
V
mA
mA
T
ABLE
4C. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, V
CCO
= 3.3V±5%
OR
2.5V±5%, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
InputLow Current
CLK, nOE
CLK, nOE
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
-5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
150
Units
V
V
µA
µA
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCO
= 3.3V±5%, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol Parameter
V
OH
V
OL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Test Conditions
Minimum
V
CCO
- 1.4
V
CCO
- 2.0
Typical
Maximum
V
CCO
- 0.9
V
CCO
- 1.7
1.0
Units
V
V
V
V
SWING
Peak-to-Peak Output Voltage Swing
0.6
NOTE 1: Outputs terminated with 50
Ω
to V
CCO
- 2V. See "Parameter Measurement Information" section,
"Output Load Test Circuit" diagrams.
IDT
™
/ ICS
™
WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
4
ICS843002BKI-72 REV. A NOVEMBER 21, 2007
ICS843002I-72
FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
T
ABLE
4E. LVPECL DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, V
CCO
= 2.5V±5%, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol Parameter
V
OH
V
OL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Test Conditions
Minimum
V
CCO
- 1.4
V
CCO
- 2.0
Typical
Maximum
V
CCO
- 0.9
V
CCO
- 1.5
1.0
Units
V
V
V
Peak-to-Peak Output Voltage Swing
0.4
V
SWING
NOTE 1: Outputs terminated with 50
Ω
to V
CCO
- 2V. See "Parameter Measurement Information" section,
"Output Load Test Circuit" diagrams.
T
ABLE
5A. AC C
HARACTERISTICS
,
V
CC
= V
CCO
= 3.3V±5%, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol Parameter
F
OUT
t
jit(ø)
t
DJ
t
RJ
t
sk(o)
t
R
/ t
F
Output Frequency
RMS Phase Jitter, (Random);
NOTE 1
Deterministic Jitter; NOTE 2
Random Jitter, RMS; NOTE 2
Output Skew; NOTE 3, 4
Output Rise/Fall Time
20% to 80%
300
Test Conditions
122.88MHz, Integration range:
1.875MHz - 10MHz
Minimum
Typical
122.88
0.49
30
2.2
50
550
51
Maximum
Units
MHz
ps
fs
ps
ps
ps
%
odc
Output Duty Cycle
49
See Parameter Measurement Information section.
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Measured using Wavecrest SIA-3000.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
5B. AC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, V
CCO
= 2.5V±5%, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol Parameter
F
OUT
t
jit(ø)
t
DJ
t
RJ
t
sk(o)
t
R
/ t
F
Output Frequency
RMS Phase Jitter, (Random);
NOTE 1
Deterministic Jitter; NOTE 2
Random Jitter, RMS; NOTE 2
Output Skew; NOTE 3, 4
Output Rise/Fall Time
20% to 80%
300
Test Conditions
122.88MHz, Integration range:
1.875MHz - 10MHz
Minimum
Typical
122.88
0.49
30
2.2
50
550
51
Maximum
Units
MHz
ps
fs
ps
ps
ps
%
odc
Output Duty Cycle
49
See Parameter Measurement Information section.
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Measured using Wavecrest SIA-3000.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
IDT
™
/ ICS
™
WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
5
ICS843002BKI-72 REV. A NOVEMBER 21, 2007
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