Rev.4.2
_00
BATTERY PROTECTION IC
FOR 3-SERIAL-CELL PACK
S-8233B Series
The S-8233B is a series of lithium-ion rechargeable battery protection ICs
incorporating high-accuracy (±25 mV) voltage detection circuits and delay
circuits. It is suitable for a 3-serial-cell lithium-ion battery pack.
Features
(1)
Internal high-accuracy voltage detection circuit
•
Over charge detection voltage
3.80
±
0.025 V to 4.40
±
0.025 V
5 mV - step
•
Over charge release voltage
3.45
±
0.100 V to 4.40
±
0.100 V
5 mV - step
(The over charge release voltage can be selected within the range where a difference from over
charge detection voltage is 0 to 0.35 V with 50 mV - step)
•
Over discharge detection voltage
2.00
±
0.08 V to 2.80
±
0.08 V
50 mV - step
Over discharge release voltage
2.00
±
0.10 V to4.00
±
0.10 V
50 mV - step
(The over discharge release voltage can be selected within the range where a difference from over
discharge detection voltage is 0 to 1.2 V with 50 mV - step)
•
Over current detection voltage 1
0.15
±
0.015 V to 0.5
±
0.05 V
50 mV - step
(2)
(3)
(4)
(5)
(6)
(7)
(8)
High input-voltage device (absolute maximum rating: 26 V)
Wide operating voltage range:
2 V to 24 V
The delay time for every detection can be set via an external capacitor.
Three over current detection levels (protection for short-circuiting)
Internal charge/discharge prohibition circuit via the control terminal
The function for charging batteries from 0 V is available.
Low current consumption
•
Operation
50
μA
max. (+25°C)
•
Power-down
0.1
μA
max. (+25°C)
Lead-free products
(9)
Applications
Lithium-ion rechargeable battery packs
Package
Package Name
16-PIN TSSOP
Package
FT016-A
Drawing Code
Tape
FT016-A
Reel
FT016-A
Seiko Instruments Inc.
1
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233B Series
Block Diagram
Rev.4.2
_00
VCC
Reference
voltage 1
+
−
Battery 1
Over charge
Over current
2,3 delay circuit
Over current
detection
circuit
VMP
CD1
+
−
Battery 1
Over discharge
Over current1,
delay circuit
COVT
VC1
Battery 1
Over charge
+
−
Battery 2
Over charge
Over discharge
delay circuit
CDT
Control
Logic
Over charge
delay circuit
CD2
+
Battery 2
Over discharge
Reference
voltage 2
−
CCT
VC2
Battery 2
Over charge
+
−
Battery 3
Over charge
DOP
CD3
+
Battery 3
Over discharge
Reference
voltage 3
−
COP
VSS
Battery 3
Over charge
Floating
detection circuit
CTL
Figure 1
Remark
The delay time for over current detection 2 and 3 is fixed by an internal IC circuit. The delay
time cannot be changed via an external capacitor.
2
Seiko Instruments Inc.
Rev.4.2
_00
Product Name Structure
1. Product name
S−8233B
x
FT
−
BATTERY PROTECTION IC FOR 3-SERIAl-CELL PACK
S-8233B Series
TB
−
G
IC direction in tape specifications
*1
Package name (abbreviation)
FT: 16-Pin TSSOP
Serial code
Assigned from A to Z in alphabetical order
*1.
Refer to the taping specifications.
2. Product name list
Table 1
Product name / Over charge Over charge Overdischarge Overdischarge Overcurrent
0V
Conditioning CTL
Parameter
detection
release
detection release voltage detection battery
function
logic
*1
voltage
voltage1 charging
voltage
voltage
V
DU
V
CU
V
IOV1
V
CD
V
DD
function
S-8233BAFT-TB-G 4.225±0.025 V
S-8233BCFT-TB-G 4.200±0.025 V
4.225 V
*2
4.2 V
2.30±0.08 V
2.30±0.08 V
2.80±0.08 V
2.00±0.08 V
2.50±0.08 V
2.70±0.10 V
2.70±0.10 V
3.30±0.10 V
2.70±0.10 V
2.75±0.10 V
0.20±0.02 V
0.20±0.02 V
0.50±0.05 V
−
−
−
Available
Unavailable
Available
Unavailable
Available
normal
reverse
normal
reverse
normal
S-8233BBFT-TB-G 4.325±0.025 V 4.15±0.10 V
S-8233BDFT-TB-G 4.325±0.025 V 4.15±0.10 V
S-8233BEFT-TB-G 4.080±0.025 V 3.90±0.10 V
0.25±0.025 V Available
0.20±0.02 V Available
*1.
The input voltage of CTL for normal condition is changed by the CTL logic. (Please refer to
“Operation”).
*2.
Without over charge detection / release hysteresis.
Remark
Please contact our sales office for the products with the detection voltage value other than those
specified above.
Seiko Instruments Inc.
3
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233B Series
Rev.4.2
_00
Pin Configurations
16-Pin TSSOP
Top view
DOP
NC
COP
VMP
COVT
CDT
CCT
VSS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
NC
CD1
VC1
CD2
VC2
CD3
CTL
Table 2
Pin No.
1
2
3
4
5
6
7
Symbol
DOP
NC
COP
VMP
COVT
CDT
CCT
VSS
CTL
CD3
VC2
CD2
VC1
CD1
NC
VCC
Description
Connects FET gate for discharge control (CMOS output)
Non connect
*1
Connects FET gate for charge control (Nch open-drain output)
Detects voltage between VCC to VMP(Over current detection pin)
Connects capacitor for over current detection1delay circuit
Connects capacitor for over discharge detection delay circuit
Connects capacitor for over charge detection delay circuit
Negative power input, and connects negative voltage for battery 3
Charge/discharge control signal input
Battery 3 conditioning signal output
Connects battery 2 negative voltage and battery 3 positive voltage
Battery 2 conditioning signal output
Connects battery 1 negative voltage and battery 2 positive voltage
Battery 1 conditioning signal output
Non connect
*1
Figure 2
8
9
10
11
12
13
14
15
16
Positive power input and connects battery 1 positive voltage
*1.
The NC pin is electrically open. The NC pin can be connected to
VCC or VSS.
4
Seiko Instruments Inc.
Rev.4.2
_00
BATTERY PROTECTION IC FOR 3-SERIAl-CELL PACK
S-8233B Series
Absolute Maximum Ratings
Table 3
(Ta
=
25
°C
unless otherwise specified)
Item
Input voltage between VCC and VSS
Input terminal voltage
VMP Input terminal voltage
CD1 output terminal voltage
CD2 output terminal voltage
CD3 output terminal voltage
DOP output terminal voltage
COP output terminal voltage
Power dissipation
Operating ambient temperature
Sym.
V
DS
V
IN
V
VMP
V
CD1
V
CD2
V
CD3
V
DOP
V
COP
P
D
T
opr
Applied Pins
−
VC1, VC2, CTL,
CCT, CDT, COVT
VMP
CD1
CD2
CD3
DOP
COP
−
−
−
Rating
V
SS
-0.3 to V
SS
+26
V
SS
-0.3 to V
CC
+0.3
V
SS
-0.3 to V
SS
+26
VC1-0.3 to V
CC
+0.3
VC2-0.3 to V
CC
+0.3
V
SS
-0.3 to V
CC
+0.3
V
SS
-0.3 to V
CC
+0.3
V
SS
-0.3 to V
VMP
+0.3
1100
*1
-20 to +70
-40 to +125
Unit
V
V
V
V
V
V
V
V
mW
°C
°C
300 (When not mounted on board) mW
Storage temperature
T
stg
−
*1.
When mounted on board
[Mounted board]
(1) Board size : 114.3 mm
×
76.2 mm
×
t1.6 mm
(2) Board name : JEDEC STANDARD51-7
Caution The absolute maximum ratings are rated values exceeding which the product could suffer
physical damage. These values must therefore not be exceeded under any conditions.
1200
Power Dissipation P
D
(mW)
1000
800
600
400
200
0
0
50
100
150
Ambient Temperature Ta (°C)
Figure 3 Power Dissipation of Package (When Mounted on Board)
Seiko Instruments Inc.
5
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