74LVTH32245
3.3 V 32-bit bus transceiver; 3-state
Rev. 01 — 23 January 2008
Product data sheet
1. General description
The 74LVTH32245 is a high-performance BiCMOS product designed for V
CC
operation at
3.3 V. The 74LVTH32245 is a 32-bit transceiver featuring non-inverting 3-state bus
compatible outputs in both send and receive directions. The device features four output
enable (nOE) inputs for easy cascading and four send/receive (nDIR) inputs for direction
control. Pin nOE controls the outputs so that the buses are effectively isolated. Bus hold
on data inputs eliminates the need for external pull-up resistors to hold unused inputs.
2. Features
I
I
I
I
I
I
I
I
I
I
32-bit bidirectional bus interface
3-state buffers
Output capability: +64 mA and
−32
mA
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs
Live insertion and extraction permitted
Power-up 3-state
No bus current loading when output is tied to 5 V bus
Latch-up protection:
N
JESD78 Class II level A exceeds 500 mA
I
ESD protection:
N
HBM JESD22-A114E exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74LVTH32245EC
−40 °C
to +85
°C
Description
Version
SOT536-1
LFBGA96 plastic low profile fine-pitch ball grid array package;
96 balls; body 13.5
×
5.5
×
1.05 mm
Type number
NXP Semiconductors
74LVTH32245
3.3 V 32-bit bus transceiver; 3-state
4. Functional diagram
2DIR
2OE
E5
1B0
A6
1A1
1B1
B5
1A2
1B2
B6
1A3
1B3
C5
1A4
1B4
C6
1A5
1B5
D5
1A6
1B6
D6
1A7
1B7
D1
D2
H5
2A7
2B7
H2
C1
H6
2A6
2B6
H1
C2
G6
2A5
2B5
G1
B1
G5
2A4
2B4
G2
B2
F6
2A3
2B3
F1
A1
F5
2A2
2B2
F2
A2
E6
2A1
2B1
E1
2A0
2B0
E2
A3
1DIR
H3
1OE
A4
H4
A5
1A0
J3
3DIR
3OE
T3
J4
N5
3B0
J2
N6
3B1
J1
P5
3B2
K2
P6
3B3
K1
R5
3B4
L2
R6
3B5
L1
T6
3B6
M2
T5
3B7
M1
4DIR
4OE
4A0
4B0
4A1
4B1
4A2
4B2
4A3
4B3
4A4
4B4
4A5
4B5
4A6
4B6
4A7
4B7
mna476
T4
J5
3A0
N2
J6
3A1
N1
K5
3A2
P2
K6
3A3
P1
L5
3A4
R2
L6
3A5
R1
M5
3A6
T1
M6
3A7
T2
Fig 1. Logic symbol
74LVTH32245_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 23 January 2008
2 of 13
NXP Semiconductors
74LVTH32245
3.3 V 32-bit bus transceiver; 3-state
V
CC
V
CC
output
data
input
to internal circuit
001aah682
mna473
Fig 2. Schematic of each output
Fig 3. Bus hold circuit
5. Pinning information
5.1 Pinning
mna475
6
5
4
3
2
1
1A1
1A0
1A3
1A2
1A5
1A4
1A7
1A6
2A1
2A0
2A3
2A2
2A5
2A4
2A6
2A7
3A1
3A0
3A3
3A2
3A5
3A4
3A7
3A6
4A1
4A0
4A3
4A2
4A5
4A4
4A6
4A7
1OE GND VCC GND GND VCC GND 2OE 3OE GND VCC GND GND VCC GND 4OE
1DIR GND VCC GND GND VCC GND 2DIR 3DIR GND VCC GND GND VCC GND 4DIR
1B0
1B1
A
1B2
1B3
B
1B4
1B5
C
1B6
1B7
D
2B0
2B1
E
2B2
2B3
F
2B4
2B5
G
2B7
2B6
H
3B0
3B1
J
3B2
3B3
K
3B4
3B5
L
3B6
3B7
M
4B0
4B1
N
4B2
4B3
P
4B4
4B5
R
4B7
4B6
T
Fig 4. Pin configuration
5.2 Pin description
Table 2.
Symbol
nDIR (n = 1 to 4)
nOE (n = 1 to 4)
1A[0:7]
1B[0:7]
2A[0:7]
2B[0:7]
3A[0:7]
3B[0:7]
4A[0:7]
Pin description
Ball
A3, H3, J3, T3
A4, H4, J4, T4
A5, A6, B5, B6, C5, C6, D5, D6
A2, A1, B2, B1, C2, C1, D2, D1
E5, E6, F5, F6, G5, G6, H6, H5
E2, E1, F2, F1, G2, G1, H1, H2
J5, J6, K5, K6, L5, L6, M5, M6
J2, J1, K2, K1, L2, L1, M2, M1
N5, N6, P5, P6, R5, R6, T6, T5
Description
direction control
output enable input (active LOW)
input or output
input or output
input or output
input or output
input or output
input or output
input or output
74LVTH32245_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 23 January 2008
3 of 13
NXP Semiconductors
74LVTH32245
3.3 V 32-bit bus transceiver; 3-state
Table 2.
Symbol
4B[0:7]
GND
V
CC
Pin description
…continued
Ball
N2, N1, P2, P1, R2, R1, T1, T2
Description
input or output
B3, B4, D3, D4, E3, E4, G3, G4, K3, K4, ground (0 V)
M3, M4, N3, N4, R3, R4
C3, C4, F3, F4, L3, L4, P3, P4
supply voltage
6. Functional description
Table 3.
Input
nOE
L
L
H
[1]
Function selection
[1]
Input/output
nDIR
L
H
X
nAn
nAn = nBn
inputs
Z
nBn
inputs
nBn = nAn
Z
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)
[1][2]
Symbol Parameter
V
CC
V
I
V
O
I
IK
I
OK
I
O
T
stg
T
j
[1]
Conditions
[3]
Min
−0.5
−0.5
−0.5
−50
−50
-
−64
−65
-
Max
+4.6
+7.0
+7.0
-
-
128
-
+150
150
Unit
V
V
V
mA
mA
mA
mA
°C
°C
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
storage temperature
junction temperature
output in OFF or HIGH-state
V
I
< 0 V
V
O
< 0 V
output in LOW-state
output in HIGH-state
[3]
Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond indicated under
Section 8 “Recommended operating conditions”
is not implied. Exposure
to absolute-maximum-rated conditions for extended periods may affect device reliability.
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability.
The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
[2]
[3]
74LVTH32245_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 23 January 2008
4 of 13
NXP Semiconductors
74LVTH32245
3.3 V 32-bit bus transceiver; 3-state
8. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
I
OH
I
OL
Recommended operating conditions
Parameter
supply voltage
input voltage
HIGH-level output current
LOW-level output current
none
current duty cycle
≤
50 %;
f
≥
1 kHz
T
amb
∆t/∆V
P
tot
[1]
Conditions
Min
2.7
0
−32
-
-
−40
-
[1]
Typ
-
-
-
-
-
-
-
-
Max
3.6
5.5
-
32
64
+85
10
1000
Unit
V
V
mA
mA
mA
°C
ns/V
mW
ambient temperature
input transition rise and fall rate
total power dissipation
in free air
outputs enabled
-
Above 70
°C
the value of P
tot
derates linearly with 1.8 mW/K.
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
T
amb
=
−40 °C
to +85
°C
[1]
V
IK
V
IH
V
IL
V
OH
input clamping voltage
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
V
CC
= 2.7 V to 3.6 V; I
OH
=
−100 µA
V
CC
= 2.7 V; I
OH
=
−8
mA
V
CC
= 3.0 V; I
OH
=
−32
mA
V
OL
LOW-level output voltage
V
CC
= 2.7 V; I
OL
= 100
µA
V
CC
= 2.7 V; I
OL
= 24 mA
V
CC
= 3.0 V; I
OL
= 16 mA
V
CC
= 3.0 V; I
OL
= 32 mA
V
CC
= 3.0 V; I
OL
= 64 mA
I
I
input leakage current
control pins
V
CC
= 3.6 V; V
I
= V
CC
or GND
V
CC
= 0 V or 3.6 V; V
I
= 5.5 V
input/output data pins; V
CC
= 3.6 V
V
I
= 5.5 V
V
I
= V
CC
V
I
= 0 V
I
OFF
I
LO
I
O(pu/pd)
power-off leakage current
output leakage current
power-up/power-down
output current
V
CC
= 0 V; V
I
or V
O
= 0 V to 4.5 V
output HIGH; V
O
= 5.5 V; V
CC
= 3.0 V
V
CC
≤
1.2 V; V
O
= 0.5 V to V
CC
;
V
I
= GND or V
CC
; nOE = don’t care
[4]
[2]
Conditions
V
CC
= 2.7 V; I
IK
=
−18
mA
Min
−1.2
2.0
-
V
CC
−
0.2
2.4
2.0
-
-
-
-
-
-
-
-
-
−5
-
-
-
Typ
−0.85
-
-
V
CC
2.5
2.3
0.07
0.3
0.25
0.3
0.4
0.1
0.1
0.1
0.5
−0.1
0.1
75
40
Max
-
-
0.8
-
-
-
0.2
0.5
0.4
0.5
0.55
±1
10
20
10
-
±100
125
±100
Unit
V
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
µA
74LVTH32245_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 23 January 2008
5 of 13
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