74AHC02; 74AHCT02
Quad 2-input NOR gate
Rev. 03 — 7 January 2008
Product data sheet
1. General description
The 74AHC02; 74AHCT02 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard JESD7-A.
The 74AHC02; 74AHCT02 provides the quad 2-input NOR function.
2. Features
s
s
s
s
s
s
Balanced propagation delays
All inputs have a Schmitt-trigger action
Inputs accepts voltages higher than V
CC
For 74AHC02 only: operates with CMOS input levels
For 74AHCT02 only: operates with TTL input levels
ESD protection:
x
HBM JESD22-A114E exceeds 2000 V
x
MM JESD22-A115-A exceeds 200 V
x
CDM JESD22-C101C exceeds 1000 V
s
Multiple package options
s
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74AHC02D
74AHCT02D
74AHC02PW
74AHCT02PW
74AHC02BQ
74AHCT02BQ
−40 °C
to +125
°C
−40 °C
to +125
°C
TSSOP14
−40 °C
to +125
°C
Name
SO14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT402-1
SOT762-1
Type number
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5
×
3
×
0.85 mm
NXP Semiconductors
74AHC02; 74AHCT02
Quad 2-input NOR gate
4. Functional diagram
2
3
5
6
8
9
11
12
1A
1B
2A
2B
3A
3B
4A
4B
1Y
1
2
≥1
1
A
≥1
4
B
Y
mna215
2Y
4
3
5
3Y
10
6
8
9
11
12
4Y
13
≥1
10
mna216
≥1
13
001aah084
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Logic diagram (one gate)
5. Pinning information
5.1 Pinning
terminal 1
index area
1A
1Y
1A
1B
2Y
2A
2B
GND
1
2
3
4
5
6
7
001aac919
2
3
4
5
6
7
GND
3A
8
14 V
CC
13 4Y
12 4B
11 4A
10 3Y
9
3B
14 V
CC
13 4Y
12 4B
1B
2Y
2A
2B
GND
(1)
02
11 4A
10 3Y
9
8
3B
3A
1
1Y
02
001aac920
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 4. Pin configuration SO14 and TSSOP14
Fig 5. Pin configuration DHVQFN14
5.2 Pin description
Table 2.
Symbol
1Y
1A
1B
2Y
74AHC_AHCT02_3
Pin description
Pin
1
2
3
4
Description
data output
data input
data input
data output
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 7 January 2008
2 of 13
NXP Semiconductors
74AHC02; 74AHCT02
Quad 2-input NOR gate
Table 2.
Symbol
2A
2B
GND
3A
3B
3Y
4A
4B
4Y
V
CC
Pin description
…continued
Pin
5
6
7
8
9
10
11
12
13
14
Description
data input
data input
ground (0 V)
data input
data input
data output
data input
data input
data output
supply voltage
6. Functional description
Table 3.
Input nA
L
X
H
[1]
Function table
[1]
Input nB
L
H
X
Output nY
H
L
L
H = HIGH voltage level; L = LOW voltage level; X = don’t care
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
SO14 package
TSSOP14 package
DHVQFN14 package
[1]
[2]
[3]
[4]
Conditions
Min
−0.5
−0.5
Max
+7.0
+7.0
-
±20
±25
75
-
+150
500
500
500
Unit
V
V
mA
mA
mA
mA
mA
°C
mW
mW
mW
V
I
<
−0.5
V
V
O
<
−0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
−0.5
V to (V
CC
+ 0.5 V)
[1]
[1]
−20
-
-
-
−75
−65
T
amb
=
−40 °C
to +125
°C
[2]
[3]
[4]
-
-
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
P
tot
derates linearly with 8 mW/K above 70
°C.
P
tot
derates linearly with 5.5 mW/K above 60
°C.
P
tot
derates linearly with 4.5 mW/K above 60
°C.
© NXP B.V. 2008. All rights reserved.
74AHC_AHCT02_3
Product data sheet
Rev. 03 — 7 January 2008
3 of 13
NXP Semiconductors
74AHC02; 74AHCT02
Quad 2-input NOR gate
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
CC
V
I
V
O
T
amb
∆t/∆V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise
and fall rate
V
CC
= 3.3 V
±
0.3 V
V
CC
= 5.0 V
±
0.5 V
Conditions
74AHC02
Min
2.0
0
0
−40
-
-
Typ
5.0
-
-
+25
-
-
Max
5.5
5.5
V
CC
+125
100
20
74AHCT02
Min
4.5
0
0
−40
-
-
Typ
5.0
-
-
+25
-
-
Max
5.5
5.5
V
CC
+125
-
20
V
V
V
°C
ns/V
ns/V
Unit
9. Static characteristics
Table 6.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
For type 74AHC02
V
IH
HIGH-level
input voltage
V
CC
= 2.0 V
V
CC
= 3.0 V
V
CC
= 5.5 V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V
V
CC
= 3.0 V
V
CC
= 5.5 V
V
OH
HIGH-level
V
I
= V
IH
or V
IL
output voltage
I
O
=
−50 µA;
V
CC
= 2.0 V
I
O
=
−50 µA;
V
CC
= 3.0 V
I
O
=
−50 µA;
V
CC
= 4.5 V
I
O
=
−4.0
mA; V
CC
= 3.0 V
I
O
=
−8.0
mA; V
CC
= 4.5 V
V
OL
LOW-level
V
I
= V
IH
or V
IL
output voltage
I
O
= 50
µA;
V
CC
= 2.0 V
I
O
= 50
µA;
V
CC
= 3.0 V
I
O
= 50
µA;
V
CC
= 4.5 V
I
O
= 4.0 mA; V
CC
= 3.0 V
I
O
= 8.0 mA; V
CC
= 4.5 V
I
I
I
CC
C
I
input leakage
current
V
I
= 5.5 V or GND;
V
CC
= 0 V to 5.5 V
1.5
2.1
3.85
-
-
-
1.9
2.9
4.4
2.58
3.94
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2.0
3.0
4.5
-
-
0
0
0
-
-
-
-
3.0
-
-
-
0.5
0.9
1.65
-
-
-
-
-
0.1
0.1
0.1
0.36
0.36
0.1
2.0
10
1.5
2.1
3.85
-
-
-
1.9
2.9
4.4
2.48
3.8
-
-
-
-
-
-
-
-
-
-
-
0.5
0.9
1.65
-
-
-
-
-
0.1
0.1
0.1
0.44
0.44
1.0
20
10
1.5
2.1
3.85
-
-
-
1.9
2.9
4.4
2.4
3.7
-
-
-
-
-
-
-
-
-
-
-
0.5
0.9
1.65
-
-
-
-
-
0.1
0.1
0.1
0.55
0.55
2.0
40
10
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
pF
Conditions
Min
25
°C
Typ
Max
−40 °C
to +85
°C −40 °C
to +125
°C
Unit
Min
Max
Min
Max
supply current V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 5.5 V
input
capacitance
74AHC_AHCT02_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 7 January 2008
4 of 13
NXP Semiconductors
74AHC02; 74AHCT02
Quad 2-input NOR gate
Table 6.
Static characteristics
…continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
For type 74AHCT02
V
IH
V
IL
V
OH
HIGH-level
input voltage
LOW-level
input voltage
V
CC
= 4.5 V to 5.5 V
V
CC
= 4.5 V to 5.5 V
2.0
-
-
-
-
0.8
2.0
-
-
0.8
2.0
-
-
0.8
V
V
Conditions
Min
25
°C
Typ
Max
−40 °C
to +85
°C −40 °C
to +125
°C
Unit
Min
Max
Min
Max
HIGH-level
V
I
= V
IH
or V
IL
; V
CC
= 4.5 V
output voltage
I
O
=
−50 µA
I
O
=
−8.0
mA
LOW-level
V
I
= V
IH
or V
IL
; V
CC
= 4.5 V
output voltage
I
O
= 50
µA
I
O
= 8.0 mA
input leakage
current
V
I
= 5.5 V or GND;
V
CC
= 0 V to 5.5 V
4.4
3.94
-
-
-
-
-
4.5
-
0
-
-
-
-
-
-
0.1
0.36
0.1
2.0
1.35
4.4
3.8
-
-
-
-
-
-
-
0.1
0.44
1.0
20
1.5
4.4
3.7
-
-
-
-
-
-
-
0.1
0.55
2.0
40
1.5
V
V
V
V
µA
µA
mA
V
OL
I
I
I
CC
∆I
CC
supply current V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 5.5 V
additional
per input pin;
supply current V
I
= V
CC
−
2.1 V; I
O
= 0 A;
other pins at V
CC
or GND;
V
CC
= 4.5 V to 5.5 V
input
capacitance
C
I
-
3.0
10
-
10
-
10
pF
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; For test circuit see
Figure 7.
Symbol Parameter
For type 74AHC02
t
pd
propagation
delay
nA, nB to nY; see
Figure 6
V
CC
= 3.0 V to 3.6 V
C
L
= 15 pF
C
L
= 50 pF
V
CC
= 4.5 V to 5.5 V
C
L
= 15 pF
C
L
= 50 pF
C
PD
power
C
L
= 50 pF; f
i
= 1 MHz;
dissipation
V
I
= GND to V
CC
capacitance
[3]
[2]
Conditions
Min
25
°C
Typ
[1]
Max
−40 °C
to +85
°C −40 °C
to +125
°C
Unit
Min
Max
Min
Max
-
-
-
-
3.9
5.5
2.9
4.2
7.0
7.9
11.4
5.5
7.5
-
1.0
1.0
1.0
1.0
-
9.5
13
6.5
8.5
-
1.0
1.0
1.0
1.0
-
10.0
14.5
7.0
9.5
-
ns
ns
ns
ns
pF
74AHC_AHCT02_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 7 January 2008
5 of 13
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