Si3452
Q
UAD
H
IGH
- V
O L TAG E
P
ORT
C
O N T R O L L E R
FOR
P
O
E
AND
P
O
E+ PSE
S
Features
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VOUT1
INT
39
40
Each Si3452 high-voltage port
controller supports four PSE power
interfaces
Programmable current limits for PoE
(15.4 W), PoE+ (30 W), and
proprietary systems (up to 40 W) per
port
I
2
C interface requires no external
MCU for easy, low-cost management
of 4 to 48 ports by the host system
Unique mixed-signal IC high-voltage
component integration simplifies
design, lowers power dissipation,
minimizes external BOM, and
reduces PCB footprint
Internal low-R
ON
power FETs with
current-sense circuitry
Integrated transient voltage surge
suppressors
Proprietary dV/dt disconnect
sensing methods
Industrial (–40 to 85 °C) operating
temperature
Compact, 6×6 mm
2
, 40-pin QFN
RoHS-compliant package
Programmable architecture supports
IEEE 802.3af (PoE) and IEEE
802.3at (PoE+) PSEs
Programmable current limits for
PoE (350 mA) and PoE+
(600 mA), and custom limits to
850 mA
Per-port current and voltage
monitoring for sophisticated power
management and control
Power policing mode
Robust multi-point detection
Supports 1-Event and 2-Event
classification algorithms
Comprehensive, robust, fault-
protection circuitry
Supply undervoltage lockout
(UVLO)
Output current limit and short-
circuit protection
Foldback current limiting
Dual-threshold thermal overload
protection
Fault source reporting for
intelligent port management
Ordering Information:
See page 31.
Pin Assignments
40-Pin QFN
VOUT2
32
GND12
38
37
36
35
34
33
31
VEE2
30
29
28
27
DET1
DET2
RST
AD1
AD0
VEE1
1
VDD
DGND
AD0
AD1
AD2
AD2
AD3
RST
VEE3
AD3
VEE
2
3
4
5
6
7
VREF
AIN
AOUT
Applications
AGND
Si3452
(Top View)
26
25
24
23
22
21
19
RBIAS
AGND
8
9
Power over Ethernet Endpoint
switches and Midspans for IEEE Std
802.3af and 802.3at
Supports high-power PDs, such as:
Pan/Tilt/Zoom security cameras
802.11n WAPs
Multi-band, multi-radio WAPs
Security and RFID systems
Industrial automation systems
Networked audio
IP Phone Systems and iPBXs
Metropolitan area networked WAPs,
cameras, and sensors
WiMAX ASN/BTS and CPE/ODU
systems
NC
VEE4
10
11
12
13
14
15
16
17
18
VDD
VOUT4
GND34
See "9. Pin Descriptions" on page 28.
Rev. 1.5 1/15
Copyright © 2015 by Silicon Laboratories
VOUT3
SDA
DET4
DET3
SCL
NC
NC
20
Si3452
Si3452
Description
When connected directly to the host system or configured in Auto mode, each Si3452 high-voltage port controller
provides all of the critical circuitry and sophisticated power measurement functionality for the high-voltage
interfaces of four complete PSE ports. The Si3452 fully integrates robust, low-R
ON
(0.3
typical) power MOSFET
switches, low-power dissipation current sensing circuitry, and transient voltage surge suppression devices.
The on-chip current sense circuitry and power MOSFETs provide programmable scaling of current limits to match
either PoE (350 mA, 15.4 W), PoE+ (600 mA, 30 W), and extended (800 mA, 40 W) power requirements on a per-
port basis. Designed for use in Endpoint PSE (e.g., Ethernet switches) or Midspan PSE (e.g., inline power
injectors) applications, each Si3452 also performs the IEEE-required powered device (PD) detection, classification,
and disconnect functionality.
The flexible architecture enables powered device disconnect detection using Silicon Laboratories' proprietary dV/dt
disconnect sensing algorithm. dV/dt disconnect is an alternative to dc disconnect that requires no additional BOM
components, does not dissipate extra device power, and fully interoperates with all powered devices. Also provided
are multi-point detection algorithms and per-port current and voltage monitoring.
Intelligent protection circuitry includes power supply undervoltage lockout (UVLO), port output current limiting and
short-circuit protection, thermal overload sensing and port shutdown, and transient voltage surge suppressors
capable of protecting the Si3452 from a variety of harsh surge events seen on the RJ-45 interface.
To maximize system design flexibility and minimize cost, each Si3452 connects directly to a system host controller
through an I
2
C serial interface, eliminating the need for an external MCU. The Si3452 can be set to one of 12
unique addresses, allowing control of up to 48 ports on a single I
2
C bus.
Functional Block Diagram
RST
AD2
AD3
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AD1
AD0
RST
AD3
AD2
AD1
GND34
MCU Core
& PSE FSM
LV SPI
HV SPI
&
Port
Control
PER PORT ANALOG
Detection
&
Classification
dV/dt
Disconnect
DET4
DET3
DET2
DET1
256 Byte SRAM
8 kByte EPROM
PLL
Temp
Sensor
POR
PGA
MEAS.
MUX
Channel
Mode
&
Limit
Control
WDT
10b
ADC
Gate Control,
Current Limit
& Foldback
AMUX
GND12
AD0
VOUT4
VOUT3
VOUT2
VOUT1
I2C
Voltage
Regulator
& Monitor
VREF & Central Bias
Thermal
Prot.
Current
Sense
VEE1
VEE2
VEE3
AGND
RBIAS
DGND
VREF
2
AGND
AOUT
VDD
Rev. 1.5
VEE4
VDD
INT
SDA
VEE
SCL
AIN
Si3452
T
ABLE O F
C
ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. PSE System-Level Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3. PSE Application Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1. Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2. Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3. Port Turn-On and Power FETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4. Disconnect Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.5. Transient Voltage Surge Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.6. Temperature Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.7. Port Measurement and Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4.8. SMBus/I
2
C Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5. Register Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
5.1. Interrupt (Registers 0x00–0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2. Port Event (Registers 0x02–0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
5.3. Port Status (Registers 0x06–0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.4. Port Configuration (Registers 0x0A–0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.5. Command and Return Registers (Registers 0x12–0x1C) . . . . . . . . . . . . . . . . . . . . .19
5.6. Device Status Register (0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6. Operational Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1. Port Turn On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
6.2. Changing the Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.3. Port Voltage and Current Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7. PCB Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
8. Firmware Release Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.1. I
2
C Address ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.2. “Sifos” Tester Vtrans_min Issue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.3. PSE-to-PSE Cross Powering Possibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
10. Package Outline: 40-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
11. Recommended PCB Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
12. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
12.1. Evaluation Kits and Reference Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
13. Device Marking Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
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Rev. 1.5
3
Si3452
1. Electrical Specifications
Unless noted otherwise, specifications apply over the operating temperature range with VDD = +3.3 V and
VEE = –48 V relative to GND.
VDD pins should be electrically shorted. AGND pins, DGND, GND12, and GND34 should be electrically shorted
(“GND”). VEE, VEE1, VEE2, VEE3, and VEE4 should be electrically shorted (“VEE”).
VPort for any port is measured from GND to the respective VOUTn.
Table 1. Absolute Maximum Ratings
1
Type
Description
VEE to GND
VDD to GND
Supply Voltages
VDD1 to VDD2
Rating
–62 to +0.3
–0.3 to +3.6
–0.3 to +0.3
–0.3 to +0.3
Unit
V
V
V
V
V
V
V
V
A
W
°C
°C
°C
Voltage on Digital Pins
Voltage on Analog Pins
DETn Peak Currents During Surge Events
2
Maximum Continuous Power Dissipation
3
Maximum Junction Temperature
Ambient Storage Temperature
Lead Temperature (Soldering, 10 seconds Maximum)
Notes:
1.
Functional operation should be restricted to those conditions specified in Table 2. Functional operation or specification
compliance is not implied at these conditions. Stresses beyond those listed in absolute maximum ratings may cause
permanent damage to the device.
2.
See IEEE Std 802.3-2005, clause 33.4, for a description of surge events.
3.
If all ports are on with 600 mA load, the power dissipation is <1.2 W. At 85 °C ambient with the expected 32 °C/W
thermal impedance, the junction temperature would be 123.4 °C, which is within the 125 °C maximum rating.
4
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Any VEE to any other VEE
Any GND to any other GND
SDA, SCL, ADn, RST, INT
VREF, AIN, AOUT, RBIAS, OSC
VOUTn, DETn
±5
1.2
125
260
Rev. 1.5
–0.3 to +0.3
(GND – 0.3) to (VDD + 0.3)
(GND – 0.3) to (VDD + 0.3)
(VEE – 0.3) to (GND + 0.3)
–55 to 150
Si3452
Table 2. Recommended Operating Conditions
Description
Ambient Operating
Temperature
Thermal Impedance*
Power Supply Voltages
For IEEE 802.3af (15.4 W) apps.
V
EE
Supply Voltage
V
DD
Supply Voltage
V
EE
V
DD
For IEEE 802.3at (30 W) apps.
–57
–57
3.0
–48
–54
3.3
–45
–51
3.6
V
V
Symbol
T
A
θ
JA
No airflow
1 m/s airflow
Test Condition
Min
–40
—
—
Typ
—
32
28
Max
85
—
°C/W
—
Unit
°C
Power Supply Currents
V
EE
Supply Current
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All ports on, excluding load current.
All ports in shutdown mode
—
I
EE
—
I
DD
—
Symbol
V
RST
Test Condition
Min
—
Ramp from 0 V to 3.0 V
—
—
0.7 x V
DD
—
—
—
RST = 0 V
—
—
T
RSTDLY
T
RST
Time between end of reset and
beginning of normal operation
—
—
RST low time to generate system
reset
Measured V
EE
relative to actual
V
EE
for V
EE
(–44 to –57 V)
Point at which VEE UVLO is
declared.
VEE going negative
VEE going positive
15
—
V
EEMON
–4
—
V
UVLO
–38
—
Rev. 1.5
3.7
1
8
6.0
mA
2
14
mA
V
DD
Supply Current
*Note:
Modeled with six parts evenly spaced on a 30 x 120 mm
2
, four-layer board with 25 thermal vias to a Vneg plane on the
back.
Table 3. UVLO, and Reset Specifications
Description
Typ
Max
—
1
—
0.8
40
100
—
4
Unit
V
ms
V
V
μA
ms
μs
%
V
DD
Reset Threshold
1.75
V
DD
Power-On Ramp
*
RST Input High Voltage
RST Input Low Voltage
RST Input Leakage
Reset Time Delay
Reset Assertion Time
V
EE
Monitor Accuracy
V
EE
UVLO Threshold
–36
–33
—
–31
V
*Note:
If VDD ramp time is slower than 1 ms, hold the reset pins low until VDD is above 3.0 V to insure proper reset
operation.
5
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