74LVTH125 — Low Voltage Quad Buffer with 3-STATE Outputs
January 2008
74LVTH125
Low Voltage Quad Buffer with 3-STATE Outputs
Features
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Input and output interface capability to systems at
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General Description
The LVTH125 contains four independent non-inverting
buffers with 3-STATE outputs.
These buffers are designed for low-voltage (3.3V) V
CC
applications, but with the capability to provide a TTL
interface to a 5V environment. The LVTH125 is fabri-
cated with an advanced BiCMOS technology to achieve
high speed operation similar to 5V ABT while maintain-
ing a low power dissipation.
5V V
CC
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs
Live insertion/extraction permitted
Power Up/Down high impedance provides glitch-free
bus loading
Outputs source/sink –32mA/+64mA
Functionally compatible with the 74 series 125
Latch-up performance exceeds 500mA
ESD performance:
– Human-body model
>
2000V
– Machine model
>
200V
– Charged-device model
>
1000V
Ordering Information
Order Number
74LVTH125M
74LVTH125SJ
74LVTH125MTC
Package
Number
M14A
M14D
MTC14
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1998 Fairchild Semiconductor Corporation
74LVTH125 Rev. 1.4.0
www.fairchildsemi.com
74LVTH125 — Low Voltage Quad Buffer with 3-STATE Outputs
Connection Diagram
Logic Symbol
IEEE/IEC
Pin Description
Pin Names
A
n
, B
n
O
n
Description
Inputs
3-STATE Outputs
Truth Table
Inputs
A
n
L
L
H
Output
B
n
L
H
X
O
n
L
H
Z
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
HIGH Impedance
©1998 Fairchild Semiconductor Corporation
74LVTH125 Rev. 1.4.0
www.fairchildsemi.com
2
74LVTH125 — Low Voltage Quad Buffer with 3-STATE Outputs
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
V
I
V
O
Supply Voltage
DC Input Voltage
DC Output Voltage
Output in 3-STATE
Parameter
Rating
–0.5V to +4.6V
–0.5V to +7.0V
–0.5V to +7.0V
–0.5V to +7.0V
–50mA
–50mA
64mA
128mA
±64mA
±128mA
–65°C to +150°C
Output in HIGH or LOW State
(1)
I
IK
I
OK
I
O
DC Input Diode Current, V
I
<
GND
DC Output Diode Current, V
O
<
GND
DC Output Current, V
O
>
V
CC
Output at HIGH State
Output at LOW State
I
CC
I
GND
T
STG
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Note:
1. I
O
Absolute Maximum Rating must be observed.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
V
I
I
OH
I
OL
T
A
∆
t /
∆
V
Supply Voltage
Input Voltage
Parameter
Min
2.7
0
Max
3.6
5.5
–32
64
Units
V
V
mA
mA
°C
ns/V
HIGH-Level Output Current
LOW-Level Output Current
Free-Air Operating Temperature
Input Edge Rate, V
IN
=
0.8V–2.0V, V
CC
=
3.0V
–40
0
85
10
©1998 Fairchild Semiconductor Corporation
74LVTH125 Rev. 1.4.0
www.fairchildsemi.com
3
74LVTH125 — Low Voltage Quad Buffer with 3-STATE Outputs
DC Electrical Characteristics
T
A
=
–40°C to +85°C
Min.
Symbol
V
IK
V
IH
V
IL
V
OH
Typ.
(2)
Max.
Units
–1.2
V
V
0.8
V
V
Parameter
Input Clamp Diode Voltage
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
V
CC
(V)
2.7
2.7–3.6
2.7–3.6
2.7–3.6
2.7
3.0
Conditions
I
I
=
–18mA
V
O
≤
0.1V or
V
O
≥
V
CC
– 0.1V
I
OH
=
–100µA
I
OH
=
–8mA
I
OH
=
–32mA
I
OL
=
100µA
I
OL
=
24mA
I
OL
=
16mA
I
OL
=
32mA
I
OL
=
64mA
2.0
V
CC
– 0.2
2.4
2.0
0.2
0.5
0.4
0.5
0.55
75
–75
500
–500
10
±1
–5
1
±100
±100
–5
5
10
0.19
5
0.19
0.19
0.2
V
OL
Output LOW Voltage
2.7
3.0
V
I
I(HOLD)
I
I(OD)
I
I
Bushold Input Minimum Drive
Bushold Input Over-Drive
Current to Change State
Input Current
Control Pins
Data Pins
3.0
3.0
3.6
3.6
3.6
0
0–1.5
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
V
I
=
0.8V
V
I
=
2.0V
(3)
(4)
µA
µA
µA
V
I
=
5.5V
V
I
=
0V or V
CC
V
I
=
0V
V
I
=
V
CC
0V
≤
V
I
or V
O
≤
5.5V
V
O
=
0.5V to 3.0V,
V
I
=
GND or V
CC
V
O
=
0.5V
V
O
=
3.0V
V
CC
<
V
O
≤
5.5V
Outputs HIGH
Outputs LOW
Outputs Disabled
V
CC
≤
V
O
≤
5.5V,
Outputs Disabled
One Input at V
CC
– 0.6V,
Other Inputs at V
CC
or
GND
I
OFF
I
PU/PD
I
OZL
I
OZH
I
OZH
+
I
CCH
I
CCL
I
CCZ
I
CCZ
+
∆I
CC
Power Off Leakage Current
Power up/down 3-STATE
Output Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
Power Supply Current
Power Supply Current
Power Supply Current
Power Supply Current
Increase in Power Supply
Current
(5)
µA
µA
µA
µA
µA
mA
mA
mA
mA
mA
Notes:
2. All typical values are at V
CC
=
3.3V, T
A
=
25°C.
3. An external driver must source at least the specified current to switch from LOW-to-HIGH.
4. An external driver must sink at least the specified current to switch from HIGH-to-LOW.
5. This is the increase in supply current for each input that is at the specified voltage level rather than V
CC
or GND.
©1998 Fairchild Semiconductor Corporation
74LVTH125 Rev. 1.4.0
www.fairchildsemi.com
4
74LVTH125 — Low Voltage Quad Buffer with 3-STATE Outputs
Dynamic Switching Characteristics(6)
Conditions
Symbol
V
OLP
V
OLV
T
A
=
25°C
Min.
Typ.
0.8
–0.8
Parameter
Quiet Output Maximum
Dynamic V
OL
Quiet Output Minimum
Dynamic V
OL
V
CC
(V) C
L
=
50 pF, R
L
=
500Ω
3.3
3.3
(7)
Max.
Units
V
V
(7)
Notes:
6. Characterized in SOIC package. Guaranteed parameter, but not tested.
7. Max number of outputs defined as (n). n–1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
T
A
=
–40°C to +85°C,
C
L
=
50pF, R
L
=
500Ω
V
CC
=
3.3V ± 0.3V
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
OSHL
, t
OSLH
Output to Output Skew
(9)
Notes:
8. All typical values are at V
CC
=
3.3V, T
A
=
25°C.
9. Skew is defined as the absolute value of the difference between the actual propagation delay for any two
separate outputs of the same device. The specification applies to any outputs switching in the same direction,
either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
).
Output Disable Time
Output Enable Time
V
CC
=
2.7V
Min.
1.0
1.0
1.0
1.1
1.5
1.3
Parameter
Propagation Delay, Data to Output
Min.
1.0
1.0
1.0
1.1
1.5
1.3
Typ.
(8)
Max.
3.5
3.9
4.0
4.0
4.5
4.5
1.0
Max.
4.5
4.9
5.5
5.4
5.7
4.0
1.0
Units
ns
ns
ns
ns
Capacitance
(10)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
V
CC
=
0V, V
I
=
0V or V
CC
V
CC
=
3.0V, V
O
=
0V or V
CC
Typical
4
8
Units
pF
pF
Note:
10. Capacitance is measured at frequency f
=
1MHz, per MIL-STD-883B, Method 3012.
©1998 Fairchild Semiconductor Corporation
74LVTH125 Rev. 1.4.0
www.fairchildsemi.com
5
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