January 2007
H Y S6 4D 64 020H B DL – 5 – C
H Y S6 4D 64 020G B DL – 5 – C
H Y S6 4D 64 020H B DL – 6 – C
H Y S6 4D 64 020G B DL – 6 – C
200-Pin Small Outline Dual-In-Line Memory Modules
SO-DIMM
DDR SDRAM
Internet Data Sheet
Rev. 1.21
Internet Data Sheet
HYS64D64020[H/G]BDL–[5/6]–C
Small Outline DDR SDRAM Modules
HYS64D64020HBDL–5–C, HYS64D64020GBDL–5–C, HYS64D64020HBDL–6–C, HYS64D64020GBDL–6–C
Revision History: 2007-01, Rev. 1.21
Page
All
All
Subjects (major changes since last revision)
Qimonda update
Adapted internet edition
Previous Revision: 2005-09, Rev. 1.2
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03292006-F1IB-1I3E
2
Internet Data Sheet
HYS64D64020[H/G]BDL–[5/6]–C
Small Outline DDR SDRAM Modules
1
1.1
Overview
Features
• Programmable CAS Latency, Burst Length, and Wrap
Sequence (Sequential & Interleave)
• Auto Refresh (CBR) and Self Refresh
• RAS-lockout Supported
t
RAP
=
t
RCD
• All Inputs and Outputs SSTL_2 Compatible
• Serial Presence Detect with E
2
PROM
• Jedec Standard form Factor:
67.60 mm
×
31.75 mm
×
3.80 mm
• Gold Plated Contacts
This chapter lists all main features of the product family HYS64D64020[H/G]BDL–[5/6]–C and the ordering information.
• Non-parity 200-Pin Small Outline Dual-In-Line Memory
Modules
• Two ranks 64M
×
64 Organization
• JEDEC standard Double Data Rate Synchronous DRAMs
(DDR SDRAM)
• Single +2.5 V (± 0.2 V) Power Supply and Single +2.6 V
(± 0.1 V) Power Supply for DDR400
• Built with 256 Mbit DDR SDRAMs Organised as
×
8 in
P–TFBGA–60 Packages
TABLE 1
Performance
Part Number Speed Code
Speed Grade
Max. Clock Frequency
Component
Module
@CL3
@CL2.5
@CL2
–5
DDR400B
PC3200–3033
–6
DDR333B
PC2700–2533
166
166
133
Unit
—
—
MHz
MHz
MHz
f
CK3
f
CK2.5
f
CK2
200
166
133
Rev. 1.21, 2007-01
03292006-F1IB-1I3E
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Internet Data Sheet
HYS64D64020[H/G]BDL–[5/6]–C
Small Outline DDR SDRAM Modules
1.2
Description
capacitors are mounted on the PC board. The DIMMs feature
serial presence detect based on a serial E
2
PROM device
using the 2-pin I
2
C protocol. The first 128 bytes are
programmed with configuration data and the second
128 bytes are available to the customer.
The HYS64D64020HBDL–5–C and HYS64D64020GBDL–5–
C are industry standard 200-Pin Small Outline Dual-In-Line
Memory Modules (SO-DIMMs) organized as 64M
×64.
The
memory array is designed with Double Data Rate
Synchronous DRAMs (DDR SDRAM). A variety of decoupling
TABLE 2
Ordering Information
Type
PC3200 (CL=3.0)
HYS64D64020GBDL–5–C
PC2700 (CL=2.5)
HYS64D64020GBDL–6–C
PC2700S–2533–0–Z
Two ranks 512 MB SO-DIMM
32 MBit (×8)
PC3200S–3033–1–Z
Two ranks 512 MB SO-DIMM
32 MBit (×8)
Compliance Code
Description
SDRAM
Technology
TABLE 3
Ordering Information for RoHS Compliant Products
Product Type
1)
PC3200 (CL=3.0)
HYS64D64020HBDL–5–C
PC2700 (CL=2.5)
HYS64D64020HBDL–6–C
PC2700S–2533–0–Z
Two ranks 512 MB SO-DIMM
32 MBit (×8)
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Compliance Code
PC3200S–3033–1–Z
Description
Two ranks 512 MB SO-DIMM
SDRAM Technology
32 MBit (×8)
Notes
1. All part numbers end with a place code designating the silicon-die revision. Reference information available on request.
Example: HYS64D32020GDL-6-B, indicating rev. B dies are used for SDRAM components.
2. The Compliance Code is printed on the module labels describing the speed sort (for example “PC2700”), the latencies and
SPD code definition (for example “2033–0” means CAS latency of 2.0 clocks, RCD
1)
latency of 3 clocks, Row Precharge
latency of 3 clocks, and JEDEC SPD code definiton version 0), and the Raw Card used for this module.
1) RCD: Row-Column-Delay
Rev. 1.21, 2007-01
03292006-F1IB-1I3E
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Internet Data Sheet
HYS64D64020[H/G]BDL–[5/6]–C
Small Outline DDR SDRAM Modules
2
Pin Configuration
explained in
Table 5
and
Table 6
respectively. The pin
numbering is depicted in
Figure 1.
The pin configuration of the Unbuffered Small Outline DDR
SDRAM DIMM is listed by function in
Table 4
(184 pins). The
abbreviations used in columns Pin and Buffer Type are
TABLE 4
Pin Configuration of SO-DIMM
Pin#
Clock Signals
35
160
89
CK0
CK1
CK2
NC
37
158
91
CK0
CK1
CK2
NC
96
95
CKE0
CKE1
NC
Control Signals
121
122
S0
S1
NC
118
120
119
117
116
RAS
CAS
WE
BA0
BA1
I
I
NC
I
I
I
I
I
SSTL
SSTL
—
SSTL
SSTL
SSTL
SSTL
SSTL
Chip Select Rank 0
Chip Select Rank 1
Note: 2-ranks module
Note: 1-rank module
Row Address Strobe
Column Address Strobe
Write Enable
Bank Address Bus 1:0
I
I
I
NC
I
I
I
NC
I
I
NC
SSTL
SSTL
SSTL
—
SSTL
SSTL
SSTL
—
SSTL
SSTL
—
Clock Signal
Clock Signal
Clock Signal
Note: ECC type module
Note: Non-ECC type module
Complement Clock
Complement Clock
Complement Clock
Note: ECC type module
Note: Non-ECC type module
Clock Enable Rank 0
Clock Enable Rank 1
Note: 2-rank module
Note: 1-rank module
Name
Pin
Type
Buffer
Type
Function
Address Signals
Rev. 1.21, 2007-01
03292006-F1IB-1I3E
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