• Any combination of sectors can be erased. Also supports
full chip erase.
Minimum 100,000 Write/Erase Cycles Minimum
Organized as 2Mx16; User Configurable as 2 x 2Mx8
Commercial, Industrial, and Military Temperature Ranges
5 Volt Read and Write. 5V
±
10% Supply.
Low Power CMOS
PRELIMINARY*
s
Data Polling and Toggle Bit feature for detection of program
or erase cycle completion.
s
Supports reading or programming data to a sector not being
erased.
s
Built-in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation.
s
RESET pin resets internal state machine to the read mode.
s
Ready/Busy (RY/BY) output for detection of program or
erase cycle completion.
s
Multiple Ground Pins for Low Noise Operation
* This data sheet describes a product under development, not fully
characterized, and is subject to change without notice.
* * Package to be developed.
Note: For programming information refer to Flash Programming 16M5
Application Notes.
s
s
s
s
s
FIG. 1
PIN CONFIGURATIONS
WF2M16-XDAX5
56 CSOP
WF2M16-XXX5
44 CSOJ (DL)**
44 FLATPACK (FL)**
PIN DESCRIPTION
I/O
0-15
A
0-20
Data Inputs/Outputs
Address Inputs
Write Enable
Chip Select
Output Enable
Power Supply
Ground
Ready/Busy
Reset
TOP VIEW
CS1
A12
A13
A14
A15
NC
CS2
NC
A20
A19
A18
A17
A16
V
CC
GND
I/O6
I/O14
I/O7
I/O15
RY/BY
OE
WE
NC
I/O13
I/O5
I/O12
I/O4
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NC
RESET
A11
A10
A9
A1
A2
A3
A4
A5
A6
A7
GND
A8
V
CC
I/O9
I/O1
I/O8
I/O0
A0
NC
NC
NC
I/O2
I/O10
I/O3
I/O11
GND
TOP VIEW
A15
A14
A13
A12
A11
A10
A9
A8
RESET
CS1
V
CC
V
SS
CS2
RY/BY
A7
A6
A5
A4
A3
A2
A1
A0
WE
A16
A17
A18
A19
A20
OE
I/O7
I/O6
I/O5
I/O4
V
SS
V
CC
I/O3
I/O2
I/O1
I/O0
WE
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
CS
1-2
OE
V
CC
V
SS
RY/BY
RESET
BLOCK DIAGRAM
I/O
0-7
RESET
WE
OE
A
0-20
RY/BY
I/O
8-15
2M x 8
2M x 8
** Package to be developed.
CS
1
CS
2
NOTE:
1. RY/BY is an open drain output and should be pulled up to Vcc
with an external resistor.
2. Address compatible with Intel 2M8 56 SSOP.
August 2001 Rev. 4
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WF2M16-XXX5
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on Any Pin Relative to V
SS
Power Dissipation
Storage Temperature
Short Circuit Output Current
Data Retention (Mil Temp)
Endurance - write/erase cycles
(Mil Temp)
Symbol
V
T
P
T
Tstg
I
OS
Ratings
-2.0 to +7.0
8
-65 to +125
100
20
100,000 min.
Unit
V
W
°C
mA
years
cycles
Parameter
OE capacitance
WE capacitance
CS capacitance
Data I/O capacitance
Address input capacitance
CAPACITANCE
(T
A
= +25°C)
Symbol
C
OE
C
WE
C
CS
C
I/O
C
AD
Conditions
V
IN
= 0 V, f = 1.0 MHz
V
IN
= 0 V, f = 1.0 MHz
V
IN
= 0 V, f = 1.0 MHz
V
I/O
= 0 V, f = 1.0 MHz
V
IN
= 0 V, f = 1.0 MHz
Max
25
25
15
15
25
Unit
pF
pF
pF
pF
pF
This parameter is guaranteed by design but not tested.
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Operating Temperature (Mil.)
Operating Temperature (Ind.)
Symbol
V
CC
V
SS
V
IH
V
IL
T
A
T
A
Min
4.5
0
2.0
-0.5
-55
-40
Typ
5.0
0
-
-
-
-
Max
5.5
0
V
CC
+ 0.5
+0.8
+125
+85
Unit
V
V
V
V
°C
°C
DC CHARACTERISTICS - CMOS COMPATIBLE
(V
CC
= 5.0V, V
SS
= 0V, T
A
= -55°C to +125°C)
Parameter
Input Leakage Current
Output Leakage Current
V
CC
Active Current for Read (1)
V
CC
Active Current for Program or Erase (2)
V
CC
Standby Current
Output Low Voltage
Output High Voltage
Low V
CC
Lock-Out Voltage
Symbol
I
LI
I
LO
I
CC1
I
CC2
I
CC3
V
OL
V
OH
V
LKO
Conditions
V
CC
= 5.5, V
IN
= GND to V
CC
V
CC
= 5.5, V
IN
= GND to V
CC
CS = V
IL
, OE = V
IH
, f = 5MHz
CS = V
IL
, OE = V
IH
V
CC
= 5.5, CS = V
IH
, f = 5MHz, RESET = Vcc
±
0.3V
I
OL
= 12.0 mA, V
CC
= 4.5
I
OH
= -2.5 mA, V
CC
= 4.5
0.85xV
cc
3.2
4.2
Min
Max
10
10
80
120
4.0
0.45
Unit
µA
µA
mA
mA
mA
V
V
V
NOTES:
1. The Icc current listed includes both the DC operating current and the frequency dependent component (@ 5MHz). The frequency component typically is less than
2mA/MHz, with OE at V
IH
.
2. Icc active while Embedded Algorithm (program or erase) is in progress.
3. DC test conditions V
IL
= 0.3V, V
IH
= V
CC
- 0.3V
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
2
WF2M16-XXX5
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS - WE CONTROLLED
(V
CC
= 5.0V, T
A
= -55°C to +125°C)
Parameter
Write Cycle Time
Chip Select Setup Time
Write Enable Pulse Width
Address Setup Time
Data Setup Time
Data Hold Time
Address Hold Time
Write Enable Pulse Width High
Duration of Byte Programming Operation (1)
Sector Erase (2)
Read Recovery Time before Write
V
CC
Setup Time
Chip Programming Time
Chip Erase Time (3)
Output Enable Hold Time (4)
RESET Pulse Width
NOTES:
1. Typical value for t
WHWH1
is 7µs.
2. Typical value for t
WHWH2
is 1sec.
3. Typical value for Chip Erase Time is 32sec.
4. For Toggle and Data Polling.
t
OEH
t
RP
10
500
t
AVAV
t
ELWL
t
WLWH
t
AVWL
t
DVWH
t
WHDX
t
WLAX
t
WHWL
t
WHWH1
t
WHWH2
t
GHWL
t
VCS
0
50
44
256
10
500
Symbol
Min
t
WC
t
CS
t
WP
t
AS
t
DS
t
DH
t
AH
t
WPH
90
0
45
0
45
0
45
20
300
15
0
50
44
256
10
500
-90
Max
Min
120
0
50
0
50
0
50
20
300
15
0
50
44
256
-120
Max
Min
150
0
50
0
50
0
50
20
300
15
-150
Max
ns
ns
ns
ns
ns
ns
ns
ns
µs
sec
µs
µs
sec
sec
ns
ns
Unit
AC CHARACTERISTICS – READ-ONLY OPERATIONS
(V
CC
= 5.0V, T
A
= -55°C to +125°C)
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select High to Output High Z (1)
Output Enable High to Output High Z (1)
Output Hold from Addresses, CS or OE Change,
whichever is First
RESET Low to Read Mode (1)
1. Guaranteed by design, not tested.
Symbol
Min
t
AVAV
t
AVQV
t
ELQV
t
GLQV
t
EHQZ
t
GHQZ
t
AXQX
t
RC
t
ACC
t
CE
t
OE
t
DF
t
DF
t
OH
t
Ready
0
20
90
90
90
40
20
20
0
20
-90
Max
Min
120
120
120
50
30
30
0
20
-120
Max
Min
150
150
150
55
35
35
-150
Max
ns
ns
ns
ns
ns
ns
ns
µs
Unit
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WF2M16-XXX5
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS,CS CONTROLLED
(V
CC
= 5.0V, V
SS
= 0V, T
A
= -55°C to +125°C)
Parameter
Write Cycle Time
Write Enable Setup Time
Chip Select Pulse Width
Address Setup Time
Data Setup Time
Data Hold Time
Address Hold Time
Chip Select Pulse Width High
Duration of Byte Programming Operation (1)
Sector Erase Time (2)
Read Recovery Time
Chip Programming Time
Chip Erase Time (3)
Output Enable Hold Time (4)
NOTES:
1. Typical value for t
WHWH1
is 7µs.
2. Typical value for t
WHWH2
is 1sec.
3. Typical value for Chip Erase Time is 32sec.
4. For Toggle and Data Polling.
t
OEH
10
Symbol
Min
t
AVAV
t
WLEL
t
ELEH
t
AVEL
t
DVEH
t
EHDX
t
ELAX
t
EHEL
t
WHWH1
t
WHWH2
t
GHEL
0
44
256
10
t
WC
t
WS
t
CP
t
AS
t
DS
t
DH
t
AH
t
CPH
90
0
45
0
45
0
45
20
300
15
0
44
256
10
-90
Max
Min
120
0
50
0
50
0
50
20
300
15
0
44
256
-120
Max
Min
150
0
50
0
50
0
50
20
300
15
-150
Max
ns
ns
ns
ns
ns
ns
ns
ns
µs
sec
µs
sec
sec
ns
Unit
FIG. 2
AC TEST CIRCUIT
Current Source
I
OL
AC TEST CONDITIONS
Parameter
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
D.U.T.
V
Z
Typ
V
IL
= 0, V
IH
= 3.0
5
1.5
1.5
Unit
V
ns
V
V
≈
1.5V
Output Timing Reference Level
C
eff
= 50 pf
(Bipolar Supply)
CS
I
OH
Current Source
The
NOTES:
V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z
0
= 75
Ω.
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to
WE signal
rising edge of the last
simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
WE
FIG. 3
Entire programming
or erase operations
t
BUSY
RESET
t
RP
t
Ready
RY/BY
RESET TIMING DIAGRAM
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4
WF2M16-XXX5
FIG. 3
AC WAVEFORMS FOR READ OPERATIONS
t
DF
t
OH
Addresses Stable
t
RC
t
OE
t
ACC
t
CE
FDx
FCS1/FCS2
FWE
FOE
Addresses
5
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