®
Technology
SiI 1162
PanelLink Transmitter
Data Sheet
Document #
SiI-DS-0081-B
SiI
1162 PanelLink Transmitter
Data Sheet
Silicon Image, Inc.
SiI-DS-0081-B
March 2004
Application Information
To obtain the most updated Application Notes and other useful information for your design, please visit the Silicon
Image web site at www.siliconimage.com or contact your local Silicon Image sales office.
Copyright Notice
This manual is copyrighted by Silicon Image, Inc. Do not reproduce, transform to any other format, or
send/transmit any part of this documentation without the expressed written permission of Silicon Image, Inc.
Silicon Image, the Silicon Image logo, PanelLink
®
and the PanelLink
®
Digital logo are registered trademarks of
Silicon Image, Inc. TMDS
TM
is a trademark of Silicon Image, Inc. VESA
®
is a registered trademark of the Video
Electronics Standards Association. I
2
C is a trademark of Philips Semiconductor. Intel
®
is a registered trademark
of Intel Corp. DVO (Digital Video Output) is a data format defined by Intel Corporation in use by all Intel Graphics
Chipset. All other trademarks are the property of their respective holders.
Trademark Acknowledgment
Disclaimer
This document provides technical information for the user. Silicon Image, Inc. reserves the right to modify the
information in this document as necessary. The customer should make sure that they have the most recent data
sheet version. Silicon Image, Inc. holds no responsibility for any errors that may appear in this document.
Customers should take appropriate action to ensure their use of the products does not infringe upon any patents.
Silicon Image, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to
infringe upon such rights.
All information contained herein is subject to change without notice.
Revision History
Revision
A
B
Date
2/4/03
3/15/2004
ECN
ECN-DS-0081-A
200400290
Comment
First Release.
SiI1162CSU Universal part added; Fig 13,14,16 fixed;
JEDEC Pkg code updated; Part marking spec updated;
Pin 24 (CTL3/A1) fix; I
2
C Slave Addressing fix. PD#
clarification for I
2
C mode. I
2
C register descriptions defaults
clarified.
© 2003, 2004 Silicon Image. Inc.
ii
SiI-DS-0081-B
SiI
1162 PanelLink Transmitter
Data Sheet
TABLE OF CONTENTS
General Description ..................................................................................................................................... 1
SiI
1162 Pin Diagram .................................................................................................................................. 1
Functional Block Diagram ........................................................................................................................... 1
PanelLink TMDS Digital Core ..................................................................................................................... 1
I
2
C Interface, Registers and Configuration Logic ....................................................................................... 1
Data Capture Logic ..................................................................................................................................... 1
Electrical Specifications .............................................................................................................................. 1
Absolute Maximum Conditions ................................................................................................................... 1
Normal Operating Conditions ..................................................................................................................... 1
DC Digital I/O Specifications....................................................................................................................... 1
DC Specifications........................................................................................................................................ 1
AC Specifications........................................................................................................................................ 1
Input Timing Diagrams................................................................................................................................ 1
Data Mapping.............................................................................................................................................. 1
Data De-skew ............................................................................................................................................. 1
Pin Descriptions ........................................................................................................................................... 1
Input Pins .................................................................................................................................................... 1
Status Pin.................................................................................................................................................... 1
Configuration/Programming Pins................................................................................................................ 1
Input Voltage Reference Pin ....................................................................................................................... 1
Power Management Pin.............................................................................................................................. 1
Differential Signal Data Pins ....................................................................................................................... 1
Power and Ground Pins.............................................................................................................................. 1
2
I C Registers ................................................................................................................................................. 1
I
2
C Register Mapping .................................................................................................................................. 1
I
2
C Register Definitions................................................................................................................................ 1
I
2
C Slave Interface ...................................................................................................................................... 1
I
2
C Programming Sequence Example ........................................................................................................ 1
Enabling Hot Plug Detection Mode............................................................................................................. 1
RESET Description ..................................................................................................................................... 1
Design Recommendations .......................................................................................................................... 1
1.5V to 3.3V I
2
C Bus Level-Shifting ............................................................................................................ 1
Voltage Ripple Regulation .......................................................................................................................... 1
PCB Ground Planes.................................................................................................................................... 1
Decoupling Capacitors................................................................................................................................ 1
Series Damping Resistors on Parallel Inputs ............................................................................................. 1
Source Termination Resistors on Differential Outputs ............................................................................... 1
Transmitter Layout ...................................................................................................................................... 1
Recommended Circuits............................................................................................................................... 1
Packaging...................................................................................................................................................... 1
E-pad Enhancement ................................................................................................................................... 1
Determining Heat Dissipation Requirements .......................................................................................... 1
Designing with E-pad Landing Area........................................................................................................ 1
Dimensions and Marking ............................................................................................................................ 1
Ordering Information.................................................................................................................................... 1
SiI-DS-0081-B
iii
SiI
1162 PanelLink Transmitter
Data Sheet
LIST OF TABLES
Table 1. 12-bit Mode Data Mapping ............................................................................................................... 1
Table 2. DK[1:0] Increments and Effect on Setup and Hold times................................................................ 1
Table 3. Sample Programming Sequence for
SiI
1162.................................................................................. 1
Table 4. Recommended Components............................................................................................................ 1
Table 5. Routing Guidelines for DVI Traces................................................................................................... 1
LIST OF FIGURES
Figure 1
.
SiI
1162 Pin Diagram....................................................................................................................... 1
Figure 2. Functional Block Diagram ............................................................................................................... 1
Figure 3. Clock Cycle/High/Low Times in High Swing Mode ......................................................................... 1
Figure 4. Differential Transition Times............................................................................................................ 1
Figure 5.
VSYNC, HSYNC Delay Times to DE
.................................................................................................... 1
Figure 6. DE High/Low Times......................................................................................................................... 1
Figure 7. Low Swing Control and Data Setup/Hold Times to IDCK+ Differential Clock ................................ 1
Figure 8. High Swing Control and Data Setup/Hold Times to IDCK+ ............................................................ 1
Figure 9. I
2
C Data Valid Delay (driving Read Cycle data).............................................................................. 1
Figure 10. ISEL/RST# Minimum Timing......................................................................................................... 1
Figure 11. Logical Interface Options for 12-bit Mode ..................................................................................... 1
Figure 12.
SiI
1162 De-skewing Feature Timing ............................................................................................ 1
Figure 13. I
2
C Byte Read................................................................................................................................ 1
Figure 14. I
2
C Byte Write ................................................................................................................................ 1
Figure 15. I
2
C Bus Voltage Level-Shifting using Fairchild NDC7002N .......................................................... 1
Figure 16. I
2
C Bus Voltage Level Shifting using Philips GTL 2010................................................................ 1
Figure 17. Voltage Regulation using TL431 ................................................................................................... 1
Figure 18. Voltage Regulation using LM317 .................................................................................................. 1
Figure 19. Decoupling and Bypass Capacitor Placement.............................................................................. 1
Figure 20. Decoupling and Bypass Schematic .............................................................................................. 1
Figure 21. Transmitter Input Series Damping Resistors ................................................................................ 1
Figure 22. Differential Output Source Terminations ...................................................................................... 1
Figure 23. Source Termination Layout Illustration ......................................................................................... 1
Figure 24. Example of Incorrect Differential Signal Routing .......................................................................... 1
Figure 25. Example of Correct Differential Signal Routing............................................................................. 1
Figure 26. Source Termination to DVI Connector Illustration......................................................................... 1
Figure 27. Recommended Hot Plug Connection............................................................................................ 1
Figure 28. E-pad Diagram .............................................................................................................................. 1
Figure 29. 48-pin TSSOP Package Dimensions and Marking Specification ................................................. 1
iv
SiI-DS-0081-B
SiI
1162 PanelLink Transmitter
Data Sheet
February 2004
General Description
The
SiI
1162 transmitter uses PanelLink
®
Digital
technology to support displays ranging from
VGA to UXGA resolutions in a single link
interface. The
SiI
1162 transmitter uses a 12-bit
interface, taking in one half-pixel per clock edge.
Designed to accommodate ultra high speed
parallel interfaces such as the Intel DVO port,
the
SiI
1162 transmitter reduces pin count to a
bare minimum and at the same time improves
signal timing. The
SiI
1162’s innovative design
eases board design requirements as well.
PanelLink Digital technology simplifies PC
design by resolving many of the system level
issues associated with high-speed mixed signal
design, providing the system designer with a
digital interface solution that is quicker to market
and lower in cost.
Features
•
•
•
•
•
•
•
•
•
•
•
•
Scaleable Bandwidth: 25 - 165 megapixels per second
Flexible Input Clocking: Single Clock Dual edge or
Differential Clock input mode
I
2
C Slave Programming Interface
Low Voltage Interface: 3.0V to 3.6V range and 1.0 to
1.9V range
Monitor Detection supported through Hot Plug and
Receiver Detection
De-skewing Option: varies clock to data input timing
Low Power: 3.3V core operation and power down mode
Cable Distance Support: over 5 meter DVI cable
DVI 1.0 Compliant with significantly greater margin than
competitive solutions
Low pin count and smaller 48-pin TSSOP package
BIOS and driver compatible with
SiI
164 transmitter
Pb-Free Universal packaging (see page 1)
SiI
1162 Pin Diagram
EDGE/HTPLG
EXT_SWING
PVCC2
MSEN
PGND
AGND
AGND
TX1+
TX0+
PD#
TX1-
TX0-
SDA/DK0
23
GND
26
SCL/DK1
43
40
44
45
SiI
1162
48-Pin TSSO P
(Top View )
18
31
19
20
21
22
10
11
12
13
14
15
16
17
1
4
5
6
7
8
9
Figure 1
.
SiI
1162 Pin Diagram
SiI-DS-0081-B
1
CTL3/A1
D9
D8
D7
D6
D5
D4
D3
D1
D11
D10
D2
D0
GND
GND
VCC
DE
VSYNC
HSYNC
IDCK+
IDCK-
VREF
VCC
24
2
3
25
27
48
42
41
39
38
37
36
35
34
33
32
30
29
46
47
28
ISEL/RST#
PVCC1
AGND
PGND
AVCC
AVCC
TXC+
TX2+
TXC-
TX2-
FPGA/CPLD
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