SN54HC126, SN74HC126
QUADRUPLE BUS BUFFER GATES
WITH 3 STATE OUTPUTS
SCLS103E − MARCH 1984 − REVISED JULY 2003
D
Wide Operating Voltage Range of 2 V to 6 V
D
High-Current 3-State Outputs Interface
D
Directly With System Bus or Can Drive Up
To 15 LSTTL Loads
Low Power Consumption, 80-µA Max I
CC
SN54HC126 . . . J OR W PACKAGE
SN74HC126 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
D
Typical t
pd
= 11 ns
D
±6-mA
Output Drive at 5 V
D
Low Input Current of 1
µA
Max
SN54HC126 . . . FK PACKAGE
(TOP VIEW)
1OE
1A
1Y
2OE
2A
2Y
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
4OE
4A
4Y
3OE
3A
3Y
1A
1OE
NC
V
CC
4OE
1Y
NC
2OE
NC
2A
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
4A
NC
4Y
NC
3OE
NC − No internal connection
description/ordering information
These quadruple bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled
when the associated output-enable (OE) input is low.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pullup
resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
ORDERING INFORMATION
TA
PDIP − N
PACKAGE†
Tube of 25
Tube of 50
SOIC − D
−40 C 85°C
−40°C to 85 C
SOP − NS
SSOP − DB
Reel of 2500
Reel of 250
Reel of 2000
Reel of 2000
Tube of 90
TSSOP − PW
CDIP − J
−55 C 125°C
−55°C to 125 C
CFP − W
Reel of 2000
Reel of 250
Tube of 25
Tube of 150
ORDERABLE
PART NUMBER
SN74HC126N
SN74HC126D
SN74HC126DR
SN74HC126DT
SN74HC126NSR
SN74HC126DBR
SN74HC126PW
SN74HC126PWR
SN74HC126PWT
SNJ54HC126J
SNJ54HC126W
SNJ54HC126J
SNJ54HC126W
HC126
HC126
HC126
HC126
TOP-SIDE
MARKING
SN74HC126N
LCCC − FK
Tube of 55
SNJ54HC126FK
SNJ54HC126FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL PRF 38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
Copyright
2003, Texas Instruments Incorporated
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
2Y
GND
NC
3Y
3A
1
SCLS103E − MARCH 1984 − REVISED JULY 2003
SN54HC126, SN74HC126
QUADRUPLE BUS BUFFER GATES
WITH 3 STATE OUTPUTS
FUNCTION TABLE
(each buffer)
INPUTS
OE
H
H
L
A
H
L
X
OUTPUT
Y
H
L
Z
logic diagram (positive logic)
1OE
1A
1
2
3
3OE
1Y
3A
10
9
8
3Y
2OE
2A
4
5
6
4OE
2Y
4A
13
12
11
4Y
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Continuous output current, I
O
(V
O
= 0 to V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±35
mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±70
mA
Package thermal impedance,
θ
JA
(see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN54HC126, SN74HC126
QUADRUPLE BUS BUFFER GATES
WITH 3 STATE OUTPUTS
SCLS103E − MARCH 1984 − REVISED JULY 2003
recommended operating conditions (see Note 3)
SN54HC126
MIN
VCC
VIH
Supply voltage
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
VIL
VI
VO
∆t/∆v
Low-level input voltage
Input voltage
Output voltage
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
VCC = 4.5 V
VCC = 6 V
0
0
2
1.5
3.15
4.2
0.5
1.35
1.8
VCC
VCC
1000
500
400
0
0
NOM
5
MAX
6
SN74HC126
MIN
2
1.5
3.15
4.2
0.5
1.35
1.8
VCC
VCC
1000
500
400
ns
V
V
V
V
NOM
5
MAX
6
UNIT
V
High-level input voltage
Input transition rise/fall time
TA
Operating free-air temperature
−55
125
−40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
2V
IOH = −20
µA
VOH
VI = VIH or VIL
IOH = −6 mA
IOH = −7.8 mA
IOL = 20
µA
VOL
VI = VIH or VIL
IOL = 6 mA
IOL = 7.8 mA
II
IOZ
ICC
Ci
VI = VCC or 0
VO = VCC or 0
VI = VCC or 0,
IO = 0
4.5 V
6V
4.5 V
6V
2V
4.5 V
6V
4.5 V
6V
6V
6V
6V
2 V to 6 V
3
TA = 25°C
MIN
TYP
MAX
1.9
4.4
5.9
3.98
5.48
1.998
4.499
5.999
4.3
5.8
0.002
0.001
0.001
0.17
0.15
±0.1
±0.01
0.1
0.1
0.1
0.26
0.26
±100
±0.5
8
10
SN54HC126
MIN
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1000
±10
160
10
MAX
SN74HC126
MIN
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1000
±5
80
10
nA
µA
µA
pF
V
V
MAX
UNIT
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
SCLS103E − MARCH 1984 − REVISED JULY 2003
SN54HC126, SN74HC126
QUADRUPLE BUS BUFFER GATES
WITH 3 STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
2V
tpd
A
Y
4.5 V
6V
2V
ten
OE
Y
4.5 V
6V
2V
tdis
OE
Y
4.5 V
6V
2V
tt
Any
4.5 V
6V
TA = 25°C
MIN
TYP
MAX
47
14
11
57
16
12
35
17
15
28
8
6
120
24
20
120
24
20
120
24
20
60
12
10
SN54HC126
MIN
MAX
180
36
31
180
36
31
180
36
31
90
18
15
SN74HC126
MIN
MAX
150
30
26
150
30
26
150
30
26
75
15
13
ns
ns
ns
ns
UNIT
switching characteristics over recommended operating free-air temperature range, C
L
= 150 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
2V
tpd
A
Y
4.5 V
6V
2V
ten
OE
Y
4.5 V
6V
2V
tt
Any
4.5 V
6V
TA = 25°C
MIN
TYP
MAX
67
19
15
100
20
17
45
17
13
150
30
25
135
27
23
210
42
36
SN54HC126
MIN
MAX
225
45
39
202
40
36
315
63
53
SN74HC126
MIN
MAX
188
38
33
169
36
30
265
53
45
ns
ns
ns
UNIT
operating characteristics, T
A
= 25°C
PARAMETER
Cpd
Power dissipation capacitance per gate
TEST CONDITIONS
No load
TYP
45
UNIT
pF
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN54HC126, SN74HC126
QUADRUPLE BUS BUFFER GATES
WITH 3 STATE OUTPUTS
SCLS103E − MARCH 1984 − REVISED JULY 2003
PARAMETER MEASUREMENT INFORMATION
VCC
S1
RL
ten
PARAMETER
tPZH
tPZL
tPHZ
tPLZ
−−
50 pF
or
150 pF
1 kΩ
RL
1 kΩ
CL
50 pF
or
150 pF
50 pF
S1
Open
Closed
Open
Closed
Open
S2
Closed
Open
Closed
Open
Open
From Output
Under Test
CL
(see Note A)
Test
Point
S2
tdis
tpd or tt
LOAD CIRCUIT
VCC
Input
50%
tPLH
In-Phase
Output
50%
10%
tPHL
Out-of-Phase
Output
90%
50%
10%
tf
90%
tr
tPLH
50%
10%
90%
tr
VOH
VOL
50%
0V
tPHL
90%
VOH
50%
10% V
OL
tf
Output
Control
tPZL
Output
Waveform 1
(See Note B)
tPZH
Input
50%
10%
90%
90%
VCC
50%
10% 0 V
tf
Output
Waveform 2
(See Note B)
VCC
50%
50%
0V
tPLZ
≈V
CC
50%
10%
tPHZ
50%
90%
VOH
≈0
V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
tr
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR
≤
1 MHz, ZO = 50
Ω,
tr = 6 ns, tf = 6 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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•
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5
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