HY51V(S)18163HG/HGL
1M x 16Bit EDO DRAM
PRELIMINARY
DESCRIPTION
The HY51V(S)18163HG/HGL is the new generation dynamic RAM organized 1,048,576 words x 16bit.
HY51V(S)18163HG/HGL has realized higher density, higher performance and various functions by utiliz-
ing advanced CMOS process technology. The HY51V(S)18163HG/HGL offers Extended Data Out Page-
Mode as a high speed access mode. Multiplexed address inputs permit the HY51V(S)18163HG/HGL to be
packaged in standard 400mil 42pin SOJ and 44(50) pin TSOP-II. The package size provides high system
bit densities and is compatible with widely available automated testing and insertion equipment.
FEATURES
•
•
•
•
•
Extended Data Out Mode capability
Read-modify-write capability
Multi-bit parallel test capability
TTL(3.3V) compatible inputs and outputs
/RAS only, CAS-before-/RAS, Hidden and self
refresh(L-version) capability
Fast access time and cycle time
Part No
HY51V(S)18163HG/HGL-5
HY51V(S)18163HG/HGL-6
HY51V(S)18163HG/HGL-7
tRAC
50ns
60ns
70ns
•
•
•
•
•
JEDEC standard pinout
42pin plastic SOJ / 44(50)pin TSOP-II (400mil)
Single power supply of 3.3V +/- 0.3V
Battery back up operation(L-version)
2CAS byte control
•
tCAC
13ns
15ns
18ns
tRC
84ns
104ns
124ns
tHPC
20ns
25ns
30ns
•
Power dissipation
50ns
Active
Standby
684mW
60ns
612mW
70ns
540mW
•
Refresh cycle
Part No
HY51V18163HG
HY51V18163HGL
Ref
1K
1K
Normal
16ms
128ms
L-part
7.2mW(CMOS level Max)
0.83mW (L-version : Max)
ORDERING INFORMATION
Part Number
HY51V(S)18163HGJ/HG(L)J-5
HY51V(S)18163HGJ/HG(L)J-6
HY51V(S)18163HGJ/HG(L)J-7
HY51V(S)18163HGT/HG(L)T-5
HY51V(S)18163HGT/HG(L)T-6
HY51V(S)18163HGT/HG(L)T-7
(S) : Self refresh,
(L) : Low power
Access Time
50ns
60ns
70ns
50ns
60ns
70ns
Package
400mil 42pin SOJ
400mil 44(50)pin TSOP-II
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.0.1/Apr.01
HY51V(S)18163HG/HGL
PIN CONFIGURATION
V
SS
I/O15
I/O14
I/O13
I/O12
V
SS
I/O11
I/O10
I/O9
I/O8
NC
V
CC
I/O0
I/O1
I/O2
I/O3
V
CC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
A11
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
V
SS
I/O15
I/O14
I/O13
I/O12
V
SS
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
V
SS
V
CC
I/O0
I/O1
I/O2
I/O3
V
CC
I/O4
I/O5
I/O6
I/O7
NC
1
2
3
4
5
6
7
8
9
10
11
50
49
48
47
46
45
44
43
42
41
40
NC
NC
WE
RAS
A11
A10
A0
A1
A2
A3
V
CC
15
16
17
18
19
20
21
22
23
24
25
36
35
34
33
32
31
30
29
28
27
26
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
V
SS
42 Pin Plastic SOJ
44(50) Pin Plastic TSOP-II
PIN DESCRIPTION
Pin
/RAS
/UCAS, /LCAS
/WE
/OE
A0-A9
A0-A9
I/O 0- I/O 15
Vcc
Vss
NC
Function
Row Address Strobe
Column Address Strobe
Write Enable
Output Enable
Address Inputs
Refresh Address Inputs
Data Input / Output
Power (3.3V)
Ground
No connection
Rev.0.1/Apr.01
2
HY51V(S)18163HG/HGL
ABSOLUTE MAXIMUM RATINGS
Parameter
Ambient Temperature
Storage Temperature
Voltage on Any Pin relative to V
ss
Voltage on V
cc
relative to V
ss
Short Circuit Output Current
Power Dissipation
Symbol
T
A
T
STG
V
T
V
cc
I
OUT
P
T
Rating
0 ~ 70
-55 ~ 125
-0.5 ~ Vcc + 0.5
(Max 4.6V)
-0.5 ~ 4.6
50
1
Unit
o
o
C
C
V
V
mA
W
Note : Operation at or above absolute Maximum Ratings can adversely affect device reliability
Recommended DC OPERATING CONDITIONS
(TA=0 to 70
o
C)
Parameter
Power Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
V
cc
V
IH
V
IL
Min
3.0
2.0
-0.3
Typ.
3.3
-
-
Max
3.6
V
cc
+ 0.3
0.8
Unit
V
V
V
Note
Note : All voltages are referenced to Vss
The supply voltage with all Vcc pins must be on the same level. The supply voltage with all Vss pins must be on the same level
Rev.0.1/Apr.01
3
HY51V(S)18163HG/HGL
Truth Table
/RAS
H
L
L
L
L
L
L
L
L
L
L
L
L
H to L
H to L
H to L
L
/LCAS
D
L
H
L
L
H
L
L
H
L
L
H
L
H
L
L
H
/UCAS
D
H
L
L
H
L
L
H
L
L
H
L
L
L
H
L
H
/WE
D
H
H
H
L
L
L
L
L
L
H to L
H to L
H to L
D
D
D
D
/OE
D
L
L
L
D
D
D
H
H
H
L to H
L to H
L to H
D
D
D
D
Output
Open
Valid
Valid
Valid
Open
Open
Open
Undefined
Undefined
Undefined
Valid
Valid
Valid
Open
Open
Open
Open
Lower byte
Upper byte
Word
Lower byte
Upper byte
Word
Lower byte
Upper byte
Word
Lower byte
Upper byte
Word
Word
Word
Word
Word
Operation
Standby
Notes
1 ,3
Read cycle
1, 3
Early write cycle
1, 2, 3
Delayed write cycle
1, 2, 3
Read-modify-write
Cycle
1, 3
CBR refresh
or
Self refresh
(L-series)
/RAS only refresh
cycle
Read cycle
(Output disabled)
1, 3
1, 3
L
L
L
H
H
Open
1, 3
Notes :
1. H : High ( inactive) L : Low ( active) D : H or L
2. t
WCS
>= 0ns Early write cycle
twcs <
0ns
Delayed write cycle
3. Mode is determined by the OR function of the /UCAS and /LCAS (mode is set by earliest of /UCAS and /LCAS
active edge and reset by the latest of /UCAS and /LCAS inactive edge), However write operation and output
High-Z control are done independently by each /UCAS, /LCAS
ex) if /RAS = H to L, /UCAS = H, /LCAS = L, then /CAS-before-/RAS refresh cycle is selected
Rev.0.1/Apr.01
4
HY51V(S)18163HG/HGL
DC CHARACTERISTICS
(Vcc = 3.3V +/- 10%, TA=0 to 70°C)
Symbol
VOH
Output Level
Output Level voltage(Iout= -2mA)
Output Level
Output Level voltage(Iout=2mA)
50ns
ICC1
Parameter
Min
2.4
Max
Vcc
Unit
V
Note
VOL
0
-
-
-
0.4
190
170
150
V
Operating current
Average power supply operating current
( /RAS, /CAS Cycling : tRC = tRC min)
Standby current (TTL interface)
Power supply standby current
(/RAS, /CAS=VIH, Dout = High-Z)
/RAS only refresh current
Average power supply current
/RAS only refresh mode
(tRC= tRC min)
60ns
70ns
mA
1, 2
I
CC2
-
2
mA
50ns
60ns
70ns
50ns
-
-
-
-
-
-
-
-
190
170
150
185
165
145
1
150
190
170
150
400
uA
4, 5
mA
mA
uA
5
mA
1, 3
mA
2
ICC3
ICC4
EDO page mode current
Average power supply current
EDO page mode (tPC=tPC min)
CMOS interface ( /RAS, /CAS >= Vcc-0.2V, Dout = High-Z)
60ns
70ns
ICC5
Standby current ( L-version)
50ns
ICC6
-
-
-
-
/CAS-before-/RAS refresh current (tRC=tRC min)
60ns
70ns
ICC7
Battery back up operating current ( standby with CBR ref.)
(CBR refresh, tRC=31.3us, tRAS <= 0.3us, Dout = High-Z, CMOS interface)
Standby current
(RAS=V
IH
, /CAS=V
IL
, Dout=Enable)
Self refresh current
(/RAS, /CAS <=0.2V, Dout=High-Z)
Input leakage current, Any input (0V<= Vin<=4.6V)
Output leakage current, (Dout is disabled, 0V<= Vout<=4.6V)
ICC8
-
5
mA
1
ICC9
II(L)
IO(L)
-
-10
-10
250
10
10
uA
uA
uA
5
Note :
1. Icc depends on output load condition when the device is selected, Icc(max) is specified at the output open condition
2. Address can be changed once or less while /RAS=VIL
3. Address can be changed once or less while /CAS=VIH
4. /CAS = L (<=0.2) while /RAS=L (<=0.2)
5. L-Version
Rev.0.1/Apr.01
5
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