HY29F080
8 Megabit (1M x 8), 5 Volt-only, Flash Memory
KEY FEATURES
n
5 Volt Read, Program, and Erase
– Minimizes system-level power
requirements
n
High Performance
– Access times as fast as 70 ns
n
Low Power Consumption
– 15 mA typical active read current
– 30 mA typical program/erase current
– 5 µA maximum CMOS standby current
n
Compatible with JEDEC Standards
– Package, pinout and command-set
compatible with the single-supply Flash
device standard
– Provides superior inadvertent write
protection
n
Sector Erase Architecture
– Sixteen equal size sectors of 64K bytes
each
– A command can erase any combination of
sectors
– Supports full chip erase
n
Erase Suspend/Resume
– Temporarily suspends a sector erase
operation to allow data to be read from, or
programmed into, any sector not being
erased
n
Sector Group Protection
– Sectors may be locked in groups of two to
prevent program or erase operations
within that sector group
n
Temporary Sector Unprotect
– Allows changes in locked sectors
(requires high voltage on RESET# pin)
n
Internal Erase Algorithm
– Automatically erases a sector, any
combination of sectors, or the entire chip
n
Internal Programming Algorithm
– Automatically programs and verifies data
at a specified address
n
Fast Program and Erase Times
– Byte programming time: 7 µs typical
– Sector erase time: 1.0 sec typical
– Chip erase time: 16 sec typical
n
Data# Polling and Toggle Status Bits
– Provide software confirmation of
completion of program or erase
operations
n
Ready/Busy# Pin
– Provides hardware confirmation of
completion of program and erase
operations
n
Minimum 100,000 Program/Erase Cycles
n
Space Efficient Packaging
– Available in industry-standard 40-pin
TSOP and 44-pin PSOP packages
LOGIC DIAGRAM
GENERAL DESCRIPTION
The HY29F080 is an 8 Megabit, 5 volt-only CMOS
Flash memory organized as 1,048,576 (1M) bytes
of eight-bits each. The device is offered in indus-
try-standard 44-pin PSOP and 40-pin TSOP pack-
ages.
The HY29F080 can be programmed and erased
in-system with a single 5-volt V
CC
supply. Inter-
nally generated and regulated voltages are pro-
vided for program and erase operations, so that
the device does not require a high voltage power
supply to perform those functions. The device can
also be programmed in standard EPROM pro-
grammers. Access times as fast as 70ns over the
full operating voltage range of 5.0 volts ± 10% are
offered for timing compatibility with the zero wait
state requirements of high speed microprocessors.
Revision 6.1, May 2001
20
A[19:0]
RESET#
RY/BY#
CE#
OE#
WE#
DQ[7:0]
8
HY29F080
To eliminate bus contention, the HY29F080 has
separate chip enable (CE#), write enable (WE#)
and output enable (OE#) controls.
The device is compatible with the JEDEC single
power-supply Flash command set standard. Com-
mands are written to the command register using
standard microprocessor write timings, from where
they are routed to an internal state-machine that
controls the erase and programming circuits.
Device programming is performed a byte at a time
by executing the four-cycle Program Command.
This initiates an internal algorithm that automati-
cally times the program pulse widths and verifies
proper cell margin.
The HY29F080’s sector erase architecture allows
any number of array sectors to be erased and re-
programmed without affecting the data contents
of other sectors. Device erasure is initiated by
executing the Erase Command. This initiates an
internal algorithm that automatically preprograms
the array (if it is not already programmed) before
executing the erase operation. During erase
cycles, the device automatically times the erase
pulse widths and verifies proper cell margin.
To protect data in the device from accidental or
unauthorized attempts to program or erase the
device while it is in the system (e.g., by a virus),
BLOCK DIAGRAM
DQ[7:0]
the device has a Sector Group Protect function
which hardware write protects selected sector
groups. The sector group protect and unprotect
features can be enabled in a PROM programmer.
Temporary Sector Unprotect, which requires a high
voltage, allows in-system erasure and code
changes in previously protected sectors.
Erase Suspend enables the user to put erase on
hold for any period of time to read data from, or
program data to, any sector that is not selected
for erasure. True background erase can thus be
achieved. The device is fully erased when shipped
from the factory.
Addresses and data needed for the programming
and erase operations are internally latched during
write cycles, and the host system can detect
completion of a program or erase operation by
observing the RY/BY# pin, or by reading the DQ[7]
(Data# Polling) and DQ[6] (toggle) status bits.
Reading data from the device is similar to reading
from SRAM or EPROM devices. Hardware data
protection measures include a low V
CC
detector
that automatically inhibits write operations during
power transitions.
The host can place the device into the standby
mode. Power consumption is greatly reduced in
this mode.
RY/BY#
DQ[7:0]
WE#
CE#
OE#
RESET#
STATE
CONTROL
COMMAND
REGISTER
ERASE VOLTAGE
GENERATOR AND
SECTOR SWITCHES
I/O CONTROL
I/O BUFFERS
ELECTRONIC
ID
DATA LATCH
PROGRAM
VOLTAGE
GENERATOR
Y-DECODER
Y-GATING
8 Mbit FLASH
MEMORY
ARRAY
(16 x 512 Kbit
Sectors)
V
CC
A[19:0]
V
C C
DETECTOR
TIMER
ADDRESS LATCH
V
SS
X-DECODER
2
Rev. 6.1/May 01
HY29F080
PIN CONFIGURATIONS
NC
RESET#
A11
A10
A9
A8
A7
A6
A5
A4
NC
NC
A3
A2
A1
A0
DQ0
DQ1
DQ2
DQ3
V
SS
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
V
CC
CE#
A12
A13
A14
A15
A16
A17
A18
A19
NC
NC
NC
NC
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
V
CC
A19
A18
A17
A16
A15
A14
A13
A12
CE#
V
CC
NC
RESET#
A11
A10
A9
A8
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Standard
TSOP40
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
NC
NC
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
V
CC
V
SS
V
SS
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
PSOP44
NC
NC
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
V
CC
V
SS
V
SS
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Reverse
TSOP40
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A19
A18
A17
A16
A15
A14
A13
A12
CE#
V
CC
NC
RESET#
A11
A10
A9
A8
A7
A6
A5
A4
Rev. 6.1/May 01
3
HY29F080
CONVENTIONS
Unless otherwise noted, a positive logic (active
High) convention is assumed throughout this docu-
ment, whereby the presence at a pin of a higher,
more positive voltage (nominally 5VDC) causes
assertion of the signal. A ‘#’ symbol following the
signal name, e.g., RESET#, indicates that the sig-
nal is asserted in a Low state (nominally 0 volts).
Whenever a signal is separated into numbered
bits, e.g., DQ[7], DQ[6], ..., DQ[0], the family of
bits may also be shown collectively, e.g., as
DQ[7:0].
The designation 0xNNNN (N = 0, 1, 2, . . . , 9, A, .
. . , E, F) indicates a number expressed in hexa-
decimal notation. The designation 0bXXXX indi-
cates a number expressed in binary notation (X =
0, 1).
SIGNAL DESCRIPTIONS
Name
A[19:0]
DQ[7:0]
CE#
Ty p e
Inputs
Des c r ip t io n
Ad d r es s , ac t iv e Hig h . These twenty inputs select one of 1,048,576 (1M) bytes
within the array for read or write operations. A[19] is the MSB and A[0] is the
LSB.
Inputs/Outputs Dat a B u s , ac t iv e Hig h . These pins provide an 8-bit data path for read and write
Tri-state
operations.
Input
Ch ip En ab le, ac t iv e L o w. This input must be asserted to read data from or
write data to the HY 29F080. When High, the data bus is tri-stated and the device
is placed in the Standby mode.
Ou t p u t En ab le, ac t iv e L o w. This input must be asserted for read operations
and negated for write operations. When High, data outputs from the device are
disabled and the data bus pins are placed in the high impedance state.
W r i t e E n a b l e , a c t i v e L o w. Co nt r o ls w r it ing o f c o mma nd s o r c o mma nd
sequences in order to program data or erase sectors of the memory array. A
write operation takes place when WE# is asserted while CE# is Low and OE#
is High.
Har d war e Res et , ac t iv e L o w. Provides a hardware method of resetting the
HY 29F080 to the read array state. When the device is reset, it immediately
terminates any operation in progress. The data bus is tri-stated and all read/write
commands are ignored while the input is asserted. While RESET# is asserted,
the device will be in the Standby mode.
Re a d y / B u s y St a t u s . I nd ic a t e s w he t he r a w r it e o r e r a s e c o mma nd is in
progress or has been completed. RY /BY # is valid after the rising edge of the
final WE# pulse of a command sequence. It remains Low while the device is
actively programming data or erasing, and goes High when it is ready to read
array data.
5-v o lt p o wer s u p p ly.
Po wer an d s ig n al g r o u n d .
OE#
Input
WE#
Input
RESET#
Input
RY /BY #
Output
Open Drain
--
--
V
CC
V
SS
MEMORY ARRAY ORGANIZATION
The 1 MByte Flash memory array is organized into
sixteen 64 KByte blocks called
sectors
(S0, S1, . .
. , S15). A sector is the smallest unit that can be
erased. Adjacent pairs of sectors (S0/S1, S2/S3,
. . . , S14/S15) are designated as a
sector group.
A sector group is the smallest unit which can be
protected to prevent accidental or unauthorized
erasure. See ‘Bus Operations’ and ‘Command
Definitions’ sections of this document for additional
information on these functions.
Table 1 defines the sector addresses, sector group
addresses and corresponding address ranges for
the HY29F080.
4
Rev. 6.1/May 01
HY29F080
Table 1. HY29F080 Memory Array Organization
Sec t o r
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
Sec t o r
Gr o u p
SG0
SG1
SG2
SG3
SG4
SG5
SG6
SG7
Sec t o r /Sec t o r Gr o u p Ad d r es s
1
A[ 19]
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A[ 18]
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A[ 17]
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A[ 16]
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Ad d r es s Ran g e A[ 19: 0]
0x00000 - 0x0FFFF
0x10000 - 0x1FFFF
0x20000 - 0x2FFFF
0x30000 - 0x3FFFF
0x40000 - 0x4FFFF
0x50000 - 0x5FFFF
0x60000 - 0x6FFFF
0x70000 - 0x7FFFF
0x80000 - 0x8FFFF
0x90000 - 0x9FFFF
0xA0000 - 0xAFFFF
0xB0000 - 0xBFFFF
0xC0000 - 0xCFFFF
0xD0000 - 0xDFFFF
0xE0000 - 0xEFFFF
0xF0000 - 0xFFFFF
Notes:
1. A[19:16] are the sector address. A[19:17] are the sector group address.
BUS OPERATIONS
Device bus operations are initiated through the
internal command register, which consists of sets
of latches that store the commands, along with
the address and data information, if any, needed
to execute the specific command. The command
register itself does not occupy any addressable
memory location. The contents of the command
Table 2. HY29F080 Normal Bus Operations
1
Operation
Read
Write
Output Disable
CE# TTL Standby
CE# CMOS Standby
Hardware Reset (TTL Standby)
Hardware Reset (CMOS Standby)
CE#
L
L
L
H
V
CC
± 0.3V
X
X
OE#
L
H
H
X
X
X
X
WE#
H
L
H
X
X
X
X
RESET #
H
H
H
H
V
CC
± 0.3V
L
V
SS
± 0.5V
A[19:0]
A
IN
A
IN
X
X
X
X
X
DQ[7:0]
D
OUT
D
IN
High-Z
High-Z
High-Z
High-Z
High-Z
register serve as inputs to an internal state ma-
chine whose outputs control the operation of the
device. Table 2 lists the normal bus operations,
the inputs and control levels they require, and the
resulting outputs. Certain bus operations require
a high voltage on one or more device pins. Those
are described in Table 3.
Notes:
1. L = V
IL
, H = V
IH
, X = Don’t Care, D
OUT
= Data Out, D
IN
= Data In. See DC Characteristics for voltage levels.
Rev. 6.1/May 01
5
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