TB62725BP/BF/BFN
TOSHIBA Bi-CMOS Integrated Circuit Silicon Monolithic
TB62725BP,TB62725BF,TB62725BFN
8-bit Constant-Current LED Driver of the 3.3-V and 5-V Power Supply Voltage Operation
The TB62725BP/BF/BFN are comprised of constant-current
drivers designed for LEDs and LED displays. The output current
value can be set using an external resistor.
As a result, all outputs will have virtually the same current
levels.
This driver incorporates an 8-bit constant-current output, an
8-bit shift register, an 8-bit latch circuit and an 8-bit AND-gate
circuit.
These drivers have been designed using the Bi-CMOS process.
TB62725BP
TB62725BF
Features
Output current capability and number of outputs:
90 mA × 8 outputs
Constant current range: 5 to 80 mA
Application output voltage:
0.7 V (output current 5 to 80 mA)
0.4 V (output current 5 to 40 mA)
For anode-common LEDs
Input signal voltage level: 3.3-V and 5-V CMOS level (Schmitt
trigger input)
Maximum output terminal voltage: 17 V
Serial data transfer rate: 20 MHz (max, cascade connection)
Operating temperature range: T
opr
=
−40
to 85°C
Package:
Type BP:
Type BF:
Type BFN:
DIP16-P-300-2.54A
SSOP16-P-225-1.00A
SSOP16-P-225-0.65B
Weight
DIP16-P-300-2.54A: 1.11 g (typ.)
SSOP16-P-225-1.00A: 0.14 g (typ.)
SSOP16-P-225-0.65B: 0.07 g (typ.)
TB62725BFN
Package and pin layout: Pin layout and functionality are similar
to those of the TB62705C series and TB62725A series.
(Each characteristic value is different.)
Constant-current accuracy (all outputs on)
Output Voltage
>
0.4 V
=
>
0.7 V
=
Current Error
between Bits
±6%
Current Error
between ICs
±15%
Output Current
5 to 40 mA
5 to 90 mA
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2006-06-13
TB62725BP/BF/BFN
Pin Assignment
(top view)
Pin layout and functionality are similar to those of the TB62705C (each characteristic value is different.),
and TB62725A (The characteristic to be the same if the minimum current range is equal to or more than 5 mA).
GND
SERIAL-IN
CLOCK
LATCH
OUT0
OUT1
OUT2
OUT3
VDD
R-EXT
SERIAL-OUT
ENABLE
OUT7
OUT6
OUT5
OUT4
Block Diagram
OUT0
OUT1
OUT7
R-EXT
I-REG
ENABLE
Q
L
LATCH
D
L
Q
D
L
Q
D
SERIAL-IN
D
CK
Q
D
CK
Q
D
CK
Q
SERIAL-OUT
CLOCK
Truth Table
CLOCK
LATCH
ENABLE
SERIAL-IN
OUT0 --- OUT5 --- OUT7
Dn --- Dn
−
5 --- Dn
−
7
No change
Dn
+
2 --- Dn
−
3 --- Dn
−
5
Dn
+
2 --- Dn
−
3 --- Dn
−
5
Off
SERIAL-OUT
Dn
−
7
Dn
−
6
Dn
−
5
Dn
−
5
Dn
−
5
H
L
H
X
X
L
L
L
L
H
Dn
Dn
+
1
Dn
+
2
Dn
+
3
Dn
+
3
Note 1:
OUT0 to OUT7
=
On when Dn
=
H; to OUT0 to OUT7
=
Off when Dn
=
L.
In order to ensure that the level of the power supply voltage is correct, an external resistor must be
connected between R-EXT and GND.
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2006-06-13
TB62725BP/BF/BFN
Timing Diagram
n
=
0
CLOCK
0V
3.3 V/5 V
SERIAL-IN
0V
3.3 V/5 V
LATCH
0V
ENABLE
3.3 V/5 V
0V
On
OUT0
Off
Off
Off
Off
On
1
2
3
4
5
6
7
3.3 V/5 V
OUT1
Off
On
Off
Off
On
OUT3
Off
Off
Off
Off
On
OUT7
Off
On
Off
Off
3.3 V/5 V
SERIAL-OUT
0V
Warning: Latch circuit is leveled-latch circuit. Be careful because it is not triggered-latch circuit.
Note 2: The latches circuit holds data by pulling the
LATCH terminal Low.
And, when LATCH terminal is a high-level, latch circuit doesn’t hold data, and it passes from the input to
the output.
When
ENABLE
terminal is a low-level, output terminal
OUT0 to OUT7 respond to the data, and on
and off does.
Attention: This IC can be used in 3.3 V or 5.0 V. However, use the V
DD
power supply and the input level in the same
voltage system.
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2006-06-13
TB62725BP/BF/BFN
Terminal Description
Pin No.
1
2
3
4
Pin Name
GND
SERIAL-IN
CLOCK
LATCH
OUT0 to
OUT7
GND terminal for control logic.
Input terminal for serial data for data shift register.
Input terminal for clock for data shift on rising edge.
Input terminal for data strobe.
When the LATCH input is driven High, data is latched. When it is pulled Low, data is hold.
Constant-current output terminals.
Input terminal for output enable.
13
ENABLE
All outputs ( OUT0 to OUT7 ) be turned off, when the ENABLE terminal is driven High.
And are turned on, when the terminal is driven Low.
14
15
16
SERIAL-OUT
R-EXT
V
DD
Output terminal for serial data input on SERIAL-IN terminal.
Input terminal used to connect an external resistor. This regulated the output current.
3.3-V and 5-V supply voltage terminal.
Function
5 to 12
Equivalent Circuits for Inputs and Outputs
ENABLE Terminal
R (UP)
V
DD
LATCH Terminal
V
DD
100
Ω
200 kΩ
GND
GND
R (DOWN)
CLOCK, SERIAL-IN Terminal
V
DD
SERIAL-OUT Terminal
V
DD
CLOCK,
SERIAL-IN
250 kΩ
ENABLE
LATCH
100
Ω
100
Ω
100
Ω
SERIAL-OUT
GND
GND
OUT0
to
OUT7
Terminals
OUT0 to OUT7
Parasitic Diode
GND
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2006-06-13
TB62725BP/BF/BFN
Absolute Maximum Ratings
(T
opr
=
25°C)
Characteristics
Supply voltage
Input voltage
Output current
Output voltage
BP-type
(when not mounted)
BF/BFN-type
(when not mounted)
BF/BFN-type (on
PCB)
BP-type
(when not mounted)
BF/BFN-type
(when not mounted)
BF/BFN-type (on
PCB)
P
d2
0.78
R
th (j-a) 1
R
th (j-a) 2
R
th (j-a) 3
T
opr
T
stg
85
330
160
°C/W
Symbol
V
DD
V
IN
I
OUT
V
OUT
P
d1
Rating
6
Unit
V
V
mA/ch
V
−
0.2 to V
DD
+
0.2
90
−
0.2 to 17
1.47
0.37
Power
dissipation
(Note 3)
W
Thermal
resistance
(Note 3)
Operating temperature
Storage temperature
−
40 to 85
−
55 to 150
°C
°C
Note 3: BP-type: Power dissipation is delated by 11.76 mW/°C if device is mounted on PCB and ambient
temperature is above 25°C.
BF and BFN-type: Power dissipation is delated by 7.69 mW/°C if device is mounted on PCB and ambient
temperature is above 25°C. With device mounted on glass-epoxy PCB of less than 40% Cu and of
dimensions 50 mm
×
50 mm
×
1.6 mm
Recommended Operating Conditions
(T
opr
= −
40°C to 85°C unless otherwise specified)
Characteristics
Supply voltage
Output voltage
Symbol
V
DD
V
OUT
I
OUT
Output current
I
OH
I
OL
V
IH
Input voltage
V
IL
Clock frequency
LATCH pulse width
f
CLK
Cascade Connected
Each DC 1 circuit
SERIAL-OUT
SERIAL-OUT
Test Condition
Min
3
Typ.
Max
5.5
0.7
4
80
Unit
V
V
mA/ch
mA
⎯
⎯
⎯
5
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
0.7
×
V
DD
−
1
1
V
DD
+
0.15
0.3
×
V
DD
20
⎯
mA
−
0.15
⎯
50
2000
MHz
t
wLATCH
(Note 4)
⎯
I
OUT
>
20 mA
=
⎯
⎯
⎯
⎯
⎯
⎯
⎯
ns
ENABLE pulse width
t
wENABLE
t
wCLOCK
t
SETUP1
t
HOLD
t
SETUP2
I
OUT
<
20 mA
ns
3000
25
CLOCK pulse width
Set-up time for CLOCK terminal
Hold time for CLOCK terminal
Set-up time for LATCH terminal
⎯
10
10
50
ns
Note 4: When the pulse of the low level is inputted to the
ENABLE
terminal held in the high level.
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2006-06-13
FPGA/CPLD
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