TB62725BPG/BFG/BFNG
TOSHIBA BiCMOS Integrated Circuit Silicon Monolithic
TB62725BPG, TB62725BFG, TB62725BFNG
8bit ConstantCurrent LED Driver of the 3.3V and 5V Power Supply Voltage Operation
The TB62725BPG/BFG/BFNG are comprised of
constantcurrent drivers designed for LEDs and LED displays.
The output current value can be set using an external resistor.
As a result, all outputs will have virtually the same current
levels.
This driver incorporates an 8bit constantcurrent output, an
8bit shift register, an 8bit latch circuit and an 8bit ANDgate
circuit.
These drivers have been designed using the BiCMOS process.
This devices are a product for the Pb free.
TB62725BPG
Features
Output current capability and number of outputs:
90 mA × 8 outputs
Constant current range: 5 to 80 mA
Application output voltage:
0.7 V (output current 5 to 80 mA)
0.4 V (output current 5 to 40 mA)
For anodecommon LEDs
Input signal voltage level: 3.3V and 5V CMOS level (Schmitt
trigger input)
Maximum output terminal voltage: 17 V
Serial data transfer rate: 20 MHz (max, cascade connection)
Operating temperature range: T
opr
= −40 to 85°C
Package:
Type BPG:
Type BFG:
Type BFNG:
DIP16P3002.54A
SSOP16P2251.00A
SSOP16P2250.65B
TB62725BFG
TB62725BFNG
Package and pin layout: Pin layout and functionality are similar
to those of the TB62705C series and TB62725A series.
(Each characteristic value is different.)
Constantcurrent accuracy (all outputs on)
Output Voltage
>
=
0.4 V
>
=
0.7 V
Weight
DIP16P3002.54A: 1.11 g (typ.)
SSOP16P2251.00A: 0.14 g (typ.)
SSOP16P2250.65B: 0.07 g (typ.)
Current Error
between Bits
±6%
Current Error
between ICs
±15%
Output Current
5 to 40 mA
5 to 90 mA
Company Headquarters
3 Northway Lane North
Latham,
New York
12110
Toll Free: 800.984.5337
Fax:
518.785.4725
Web: www.marktechopto.com | Email: info@marktechopto.com
California Sales Office:
950 South Coast Drive, Suite 225
Costa Mesa, California 92626
Toll Free: 800.984.5337
Fax: 714.850.9314
TB62725BPG/BFG/BFNG
Pin Assignment
(top view)
Pin layout and functionality are similar to those of the TB62705C. (each characteristic value is different.)
GND
SERIALIN
CLOCK
LATCH
OUT0
OUT1
OUT2
OUT3
VDD
REXT
SERIALOUT
ENABLE
OUT7
OUT6
OUT5
OUT4
Block Diagram
OUT0
OUT1
OUT7
REXT
IREG
ENABLE
Q
L D
LATCH
Q
L D
L
Q
D
SERIALIN
D Q
CK
D Q
CK
D Q
CK
SERIALOUT
CLOCK
Truth Table
CLOCK
LATCH
H
L
H
X
X
ENABLE
L
L
L
L
H
SERIALIN
Dn
Dn
+
1
Dn
+
2
Dn
+
3
Dn
+
3
OUT0 OUT5 OUT7
Dn Dn
-
5 Dn
-
7
No change
Dn
+
2 Dn
-
3 Dn
-
5
Dn
+
2 Dn
-
3 Dn
-
5
Off
SERIALOUT
Dn
-
7
Dn
-
6
Dn
-
5
Dn
-
5
Dn
-
5
Note 1:
OUT0
to
OUT7
=
On when Dn
=
H; to
OUT0
to
OUT7
=
Off when Dn
=
L.
In order to ensure that the level of the power supply voltage is correct, an external resistor must be
connected between REXT and GND.
2
20050420
TB62725BPG/BFG/BFNG
Timing Diagram
n
=
0
CLOCK
1
2
3
4
5
6
7
3.3 V/5 V
0 V
3.3 V/5 V
SERIALIN
0 V
3.3 V/5 V
LATCH
0 V
3.3 V/5 V
0 V
On
OUT0
Off
Off
Off
Off
On
ENABLE
OUT1
Off
On
Off
Off
On
OUT3
Off
Off
Off
Off
On
OUT7
Off
On
Off
Off
3.3 V/5 V
SERIALOUT
0 V
Warning: Latch circuit is leveledlatch circuit. Be careful because it is not triggeredlatch circuit.
Note 2: The latches circuit holds data by pulling the
LATCH
terminal Low.
And, when
LATCH
terminal is a highlevel, latch circuit doesn’t hold data, and it passes from the input to
the output.
When
ENABLE
terminal is a lowlevel, output terminal
OUT0
to
OUT7
respond to the data, and on
and off does.
Attention: This IC can be used in 3.3 V or 5.0 V. However, use the V
DD
power supply and the input level in the same
voltage system.
3
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TB62725BPG/BFG/BFNG
Terminal Description
Pin No.
1
2
3
4
Pin Name
GND
SERIALIN
CLOCK
LATCH
OUT0 to
OUT7
GND terminal for control logic.
Input terminal for serial data for data shift register.
Input terminal for clock for data shift on rising edge.
Input terminal for data strobe.
When the LATCH input is driven High, data is latched. When it is pulled Low, data is hold.
Constantcurrent output terminals.
Input terminal for output enable.
13
ENABLE
All outputs ( OUT0 to OUT7 ) be turned off, when the ENABLE terminal is driven High.
And are turned on, when the terminal is driven Low.
14
15
16
SERIALOUT
REXT
V
DD
Output terminal for serial data input on SERIALIN terminal.
Input terminal used to connect an external resistor. This regulated the output current.
3.3V and 5V supply voltage terminal.
Function
5 to 12
Equivalent Circuits for Inputs and Outputs
ENABLE Terminal
R (UP)
V
DD
200 kW
LATCH Terminal
V
DD
100
W
GND
GND
R (DOWN)
CLOCK, SERIALIN Terminal
V
DD
SERIALOUT Terminal
V
DD
CLOCK,
SERIALIN
250 kW
ENABLE
LATCH
100
W
100
W
SERIALOUT
100
W
GND
GND
OUT0 to OUT7 Terminals
OUT0 to OUT7
Parasitic Diode
GND
4
20050420
TB62725BPG/BFG/BFNG
Maximum Ratings
(T
opr
=
25°C)
Characteristics
Supply voltage
Input voltage
Output current
Output voltage
BPGtype
(when not mounted)
BFG/BFNGtype
(when not mounted)
BFG/BFNGtype (on
PCB)
BPGtype
(when not mounted)
BFG/BFNGtype
(when not mounted)
BFG/BFNGtype (on
PCB)
Symbol
V
DD
V
IN
I
OUT
V
OUT
P
d1
Rating
6
-0.2 to V
DD
+
0.2
90
-0.2 to 17
1.47
0.37
P
d2
0.78
R
th (ja) 1
R
th (ja) 2
R
th (ja) 3
T
opr
T
stg
85
330
160
-40 to 85
-55 to 150
°C
°C
°C/W
W
Unit
V
V
mA/ch
V
Power
dissipation
(Note 3)
Thermal
resistance
(Note 3)
Operating temperature
Storage temperature
Note 3: BPGtype: Power dissipation is delated by 11.76 mW/°C if device is mounted on PCB and ambient
temperature is above 25°C.
BFG and BFNGtype: Power dissipation is delated by 7.69 mW/°C if device is mounted on PCB and ambient
temperature is above 25°C. With device mounted on glassepoxy PCB of less than 40% Cu and of
dimensions 50 mm
´
50 mm
´
1.6 mm
Recommended Operating Conditions
(T
opr
= -40°C to 85°C unless otherwise specified)
Characteristics
Supply voltage
Output voltage
Symbol
V
DD
V
OUT
I
OUT
Output current
I
OH
I
OL
V
IH
Input voltage
V
IL
Clock frequency
LATCH pulse width
ENABLE pulse width
(Note 4)
CLOCK pulse width
Setup time for CLOCK terminal
Hold time for CLOCK terminal
Setup time for LATCH terminal
t
w
ENABLE
t
wCLOCK
t
SETUP1
t
HOLD
t
SETUP2
¾
10
50
¾
¾
¾
¾
f
CLK
t
w
LATCH
I
OUT
>
20 mA
=
I
OUT
<
20 mA
Cascade Connected
¾
¾
Each DC 1 circuit
SERIALOUT
SERIALOUT
Test Condition
¾
¾
Min
3
¾
5
¾
¾
0.7
´
V
DD
-0.15
¾
50
2000
3000
25
10
0.7
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
Typ.
Max
5.5
4
80
-1
1
V
DD
+
0.15
0.3
´
V
DD
20
¾
¾
¾
¾
¾
ns
MHz
ns
ns
Unit
V
V
mA/ch
mA
mA
Note 4: When the pulse of the low level is inputted to the
ENABLE
terminal held in the high level.
5
20050420
FPGA/CPLD
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