64Mb Synchronous DRAM based on 1M x 4Bank x16 I/O
Document Title
4Bank x 1M x 16bits Synchronous DRAM
Revision History
Revision No.
0.01
Initial Draft
1. Editorial chage
0.80Typ --> 0.45 +/-0.05 (page12, Ball Dimension)
Before dimension :
History
Draft Date
Dec. 2004
Remark
Preliminary
0.80 Typ.
0.65 Typ.
0.2
After dimension :
June. 2005
Preliminary
0.450 +/- 0.05
0.65 Typ.
2. Added
Speed Product(100MHz CL2) (see to Page 02)
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 0.2 / June. 2005
1
Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY5V66E(L)F6(P) Series
11
Preliminary
DESCRIPTION
The Hynix HY5V66E(L)F6(P) series is a 67,108,864bit CMOS Synchronous DRAM, ideally suited for the memory appli-
cations which require wide data I/O and high bandwidth. HY5V66E(L)F6(P) is organized as 4banks of 1,048,576 x 16.
HY5V66E(L)F6(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and out-
puts are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very
high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(se-
quential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or
can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not re-
stricted by a '2N' rule)
FEATURES
•
•
•
•
•
•
Voltage: VDD, VDDQ 3.3V supply voltage
All device pins are compatible with LVTTL interface
60 Ball FBGA (Lead or Lead Free Package)
All inputs and outputs referenced to positive edge of
system clock
Data mask function by UDQM, LDQM
•
Internal four banks operation
•
Burst Read Single Write operation
Programmable CAS Latency; 2, 3 Clocks
•
•
•
Auto refresh and self refresh
4096 Refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
ORDERING INFORMATION
Part No.
HY5V66E(L)F6(P)-5
HY5V66E(L)F6(P)-6
HY5V66E(L)F6(P)-7
HY5V66E(L)F6(P)-H
HY5V66E(L)F6(P)-P
Note:
1. HY5V66EF6 Series: Normal power, Leaded.
2. HY5V66ELF6 Series: Low power, Leaded.
3. HY5V66EF6P Series: Normal power, Lead Free.
4. HY5V66ELF6P Series: Low power, Lead Free.
Clock Frequency
200MHz
166MHz
143MHz
133MHz
100MHz
CL
Organization
Interface
Package
3
4Banks x 1Mbits
x16
LVTTL
60 Ball FBGA
2
Rev. 0.2 / June. 2005
2
Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY5V66E(L)F6(P) Series
11
Preliminary
BALL CONFIGURATION
VDD
A1
A10
BA0
/CS
/CAS
/WE
NC
DQ7
DQ6
DQ5
DQ3
DQ2
DQ1
VDD
7
6
5
A3
A2
A0
BA1
NC
/RAS
LDQM
VDD
NC
VSSQ
VDDQ
DQ4
VSSQ
VDDQ
DQ0
Bottom View
4
3
A4
A5
A7
A9
NC
CLK
UDQM
VSS
NC
VDDQ
VSSQ
DQ11
VDDQ
VSSQ
DQ15
2
1
VSS
A6
A8
A11
CKE
NC
NC
NC
DQ8
DQ9
DQ10
DQ12
DQ13
DQ14
VSS
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
BALL DESCRIPTION
SYMBOL
CLK
CKE
CS
BA0, BA1
A0 ~ A11
RAS, CAS, WE
UDQM, LDQM
DQ0 ~ DQ15
V
DD
/V
SS
V
DDQ
/V
SSQ
NC
Rev. 0.2 / June. 2005
TYPE
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
I/O
SUPPLY
SUPPLY
-
DESCRIPTION
Clock: The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
Clock Enable: Controls internal clock signal and when deactivated, the SDRAM will
be one of the states among (deep) power down, suspend or self refresh
Chip Select: Enables or disables all inputs except CLK, CKE, UDQM and LDQM
Bank Address: Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address: RA0 ~ RA11, Column Address: CA0 ~ CA7
Auto-precharge flag: A10
Command Inputs: RAS, CAS and WE define the operation
Refer function truth table for details
Data Mask: Controls output buffers in read mode and masks input data in write
mode
Data Input / Output: Multiplexed data input / output pin
Power supply for internal circuits
Power supply for output buffers
No connection : These pads should be left unconnected
3
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