INTEGRATED CIRCUITS
74ABT833
Octal transceiver with parity
generator/checker (3-State)
Product data
Supersedes data of 1993 Jun 21
2002 Dec 17
Philips
Semiconductors
Philips Semiconductors
Product data
Octal transceiver with parity generator/checker
(3-State)
74ABT833
FEATURES
•
Low static and dynamic power dissipation with high speed and
high output drive
The 74ABT833 is an octal transceiver with a parity
generator/checker and is intended for bus-oriented applications.
When Output Enable A (OEA) is HIGH, it will place the A outputs in
a high impedance state. Output Enable B (OEB) controls the B
outputs in the same way.
The parity generator creates an odd parity output (PARITY) when
OEB is LOW. When OEA is LOW, the parity of the B port, including
the PARITY input, is checked for odd parity. When an error is
detected, the error data is sent to the input of a storage register. If a
LOW-to-HIGH transition happens at the clock input (CP), the error
data is stored in the register and the Open-collector error flag
(ERROR) will go LOW. The error flag register is cleared with a LOW
pulse on the CLEAR input.
If both OEA and OEB are LOW, data will flow from the A bus to the
B bus and the part is forced into an error condition which creates an
inverted PARITY output. This error condition can be used by the
designer for system diagnostics.
•
Open-collector ERROR output with flag register
•
Output capability: +64 mA / –32 mA
•
Latch-up protection exceeds 500 mA per Jedec Std 17
•
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
•
Power-up/down 3-State
•
Live insertion/extraction permitted
DESCRIPTION
The 74ABT833 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
t
PLH
t
PHL
C
IN
C
I/O
I
CCZ
PARAMETER
Propagation delay
An to Bn or Bn to An
Propagation delay
An to PARITY
Input capacitance
I/O capacitance
Total supply current
CONDITIONS
T
amb
= 25
°C;
GND = 0 V
C
L
= 50 pF; V
CC
= 5 V
C
L
= 50 pF; V
CC
= 5 V
V
I
= 0 V or V
CC
Outputs disabled; V
O
= 0 V or V
CC
Outputs disabled; V
CC
= 5.5 V
TYPICAL
3.4
7.4
4
7
50
UNIT
ns
ns
pF
pF
µA
ORDERING INFORMATION
PACKAGES
24-Pin plastic SO
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40
°C
to +85
°C
–40
°C
to +85
°C
–40
°C
to +85
°C
PART NUMBER
74ABT833D
74ABT833DB
74ABT833PW
DWG NUMBER
SOT137-1
SOT340-1
SOT355-1
PIN CONFIGURATION
OEA
1
24 V
CC
23 B0
22 B1
21 B2
20 B3
19 B4
TOP VIEW
18 B5
17 B6
16 B7
15 PARITY
14 OEB
13 CP
PIN DESCRIPTION
SYMBOL
PIN NUMBER
2, 3, 4, 5,
6, 7, 8, 9
23, 22, 21, 20,
19, 18, 17, 16
1
14
15
10
11
13
12
24
NAME AND FUNCTION
A port 3-State inputs/outputs
B port 3-State inputs/outputs
Enables the A outputs when LOW
Enables the B outputs when LOW
Parity output/input
Error output (open collector)
Clears the error flag register
when LOW
Clock input
Ground (0 V)
Positive supply voltage
A0 2
A1 3
A2 4
A3 5
A4 6
A5 7
A6 8
A7 9
ERROR 10
CLEAR 11
GND 12
A0 – A7
B0 – B7
OEA
OEB
PARITY
ERROR
CLEAR
CP
GND
V
CC
SA00212
2002 Dec 17
2
Philips Semiconductors
Product data
Octal transceiver with parity generator/checker
(3-State)
74ABT833
LOGIC SYMBOL
2
3
4
5
6
7
8
9
A0 A1 A2 A3 A4 A5 A6 A7
14
1
11
13
OEB
OEA
CLEAR
CP
B0 B1 B2 B3 B4 B5 B6 B7
PARITY
ERROR
15
10
23 22 21 20 19 18 17 16
SA00213
FUNCTION TABLE
INPUTS
MODE
A data to B bus and generate odd parity output
B data to A bus and check for parity error
1
A bus and B bus disabled
2
A data to B bus and generate inverted parity output
OEB
L
H
H
L
OEA
H
L
H
L
An
Σ
of Highs
Odd
Even
(output)
X
Odd
Even
Bn + Parity
Σ
of Highs
(output)
X
X
(output)
An
(input)
Bn
Z
(input)
OUTPUTS
Bn
An
(input)
Z
An
PARITY
L
H
(input)
Z
H
L
NOTES:
1. Error checking is detailed in the Error Flag Function Table below.
2. When clocked, the error output is LOW if the sum of A inputs is even or HIGH if the sum of A inputs is odd.
ERROR FLAG FUNCTION TABLE
INPUTS
MODE
CLEAR
H
Sample
H
H
Hold
Clear
H
L
X
NC
Z
↑
↑
=
=
=
=
=
=
=
H
L
HIGH voltage level steady state
LOW voltage level steady state
Don’t care
No change
High impedance “off” state
LOW-to-HIGH clock transition
Not a LOW-to-HIGH clock transition
CP
↑
↑
X
↑
X
Bn + Parity
Σ
of Highs
Odd
Even
X
X
X
Internal node
Point ”P”
H
L
X
X
X
Output
Pre–state
ERRORn–1
H
X
L
X
X
ERROR
OUTPUT
H
L
L
NC
H
2002 Dec 17
3
Philips Semiconductors
Product data
Octal transceiver with parity generator/checker
(3-State)
74ABT833
LOGIC DIAGRAM
8
A0 – A7
8
B0 – B7
8
OEB
PARITY
OEA
8
8
MUX
9–bit
Odd
Parity
Tree
”P”
A
}
}
B
9
Sel A/B
D
CP
CLEAR
R
ERROR
SA00214
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
V
CC
I
IK
V
I
I
OK
V
OUT
I
OUT
T
stg
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
3
DC output diode current
DC output voltage
3
DC output current
Storage temperature range
V
O
< 0 V
output in Off or HIGH state
output in LOW state
V
I
< 0 V
CONDITIONS
RATING
–0.5 to +7.0
–18
–1.2 to +7.0
–50
–0.5 to +5.5
128
–65 to 150
UNIT
V
mA
V
mA
V
mA
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150
°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2002 Dec 17
4
Philips Semiconductors
Product data
Octal transceiver with parity generator/checker
(3-State)
74ABT833
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
Min
V
CC
V
I
V
IH
V
IL
V
OH
I
OH
I
OL
∆t/∆v
T
amb
DC supply voltage
Input voltage
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage, ERROR
HIGH-level output current
LOW-level output current
Input transition rise or fall rate
Operating free-air temperature range
0
–40
4.5
0
2.0
0.8
5.5
–32
64
5
+85
LIMITS
Max
5.5
V
CC
V
V
V
V
V
mA
mA
ns/V
°C
UNIT
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25
°C
Min
V
IK
I
OH
Input clamp voltage
HIGH-level output current
ERROR ONLY
V
CC
= 4.5 V; I
IK
= –18 mA
V
CC
= 5.5 V; V
OH
= 5.5 V; V
I
= V
IL
or V
IH
V
CC
= 4.5 V; I
OH
= –3 mA; V
I
= V
IL
or V
IH
V
OH
HIGH-level output voltage
All outputs except ERROR
V
CC
= 5.0 V; I
OH
= –3 mA; V
I
= V
IL
or V
IH
V
CC
= 4.5 V; I
OH
= –32 mA; V
I
= V
IL
or V
IH
V
OL
I
I
I
OFF
I
PU
I
PD
I
IH
+ I
OZH
I
IL
+ I
OZL
I
CEX
I
O
I
CCH
I
CCL
I
CCZ
∆I
CC
Additional supply current per
input pin
2
Quiescent supply current
LOW-level output voltage
Input leakage
current
Control pins
Data pins
V
CC
= 4.5 V; I
OL
= 64 mA; V
I
= V
IL
or V
IH
V
CC
= 5.5 V; V
I
= GND or 5.5 V
V
CC
= 5.5 V; V
I
= GND or 5.5 V
V
CC
= 0.0 V; V
I
or V
O
≤
4.5 V
V
CC
= 2.0 V; or V
O
= 0.5 V; V
I
= GND or V
CC
;
V
OE
= Don’t care
V
CC
= 5.5 V; V
O
= 2.7 V; V
I
= V
IL
or V
IH
V
CC
= 5.5 V; V
O
= 0.5 V; V
I
= V
IL
or V
IH
V
CC
= 5.5 V; V
O
= 5.5 V; V
I
= GND or V
CC
V
CC
= 5.5 V; V
O
= 2.5 V
V
CC
= 5.5 V; Outputs HIGH, V
I
= GND or V
CC
V
CC
= 5.5 V; Outputs LOW, V
I
= GND or V
CC
V
CC
= 5.5 V; Outputs 3-State; V
I
= GND or V
CC
V
CC
= 5.5 V; one input at 3.4 V,
other inputs at V
CC
or GND
–50
2.5
3.0
2.0
3.5
4.0
2.6
0.42
±0.01
±5
±5.0
±5.0
5.0
–5.0
5.0
–80
50
20
50
0.3
0.55
±1.0
±100
±100
±50
50
–50
50
–180
250
30
250
1.5
–50
Typ
–0.9
Max
–1.2
20
2.5
3.0
2.0
0.55
±1.0
±100
±100
±50
50
–50
50
–180
250
30
250
1.5
T
amb
= –40
°C
to +85
°C
Min
Max
–1.2
20
V
µA
V
V
V
V
µA
µA
V
V
µA
µA
µA
mA
µA
mA
µA
mA
UNIT
Power-off leakage current
Power-up/down 3-State
output current
3
3-State output HIGH current
3-State output LOW current
Output High leakage current
Output current
1
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4 V.
3. This parameter is valid for any V
CC
between 0 V and 2.1 V, with a transition time of up to 10 msec. From V
CC
= 2.1 V to V
CC
= 5 V
±
10%, a
transition of up to 100
µsec
is permitted. The ERROR output pin 10 is not included in this spec due to the open collector design.
2002 Dec 17
5
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
