IDT74FCT377AT/CT/DT
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
INDUSTRIAL TEMPERATURE RANGE
FAST CMOS OCTAL
D FLIP-FLOP WITH
CLOCK ENABLE
FEATURES:
•
•
•
•
A, C, and D grades
Low input and output leakage
≤
1µA (max.)
CMOS power levels
True TTL input and output compatibility:
– V
OH
= 3.3V (typ.)
– V
OL
= 0.3V (typ.)
High Drive outputs (-15mA I
OH
, 48mA I
OL
)
Meets or exceeds JEDEC standard 18 specifications
Power off disable outputs permit "live insertion"
Available in SOIC and QSOP packages
IDT74FCT377AT/CT/DT
DESCRIPTION:
The IDT74FCT377T is an octal D flip-flop built using an advanced dual
metal CMOS technology. The IDT74FCT377T has eight edge-triggered,
D-type flip-flops with individual D inputs and O outputs. The common
buffered Clock (CP) input loads all flip-flops simultaneously when the Clock
Enable (CE) is low. The register is fully edge-triggered. The state of each
D input, one set-up time before the low-to-high clock transition, is transferred
to the corresponding flip-flop’s O output. The
CE
input must be stable only
one set-up time prior to the low-to-high transition for predictable operation.
•
•
•
•
FUNCTIONAL BLOCK DIAGRAM
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
CE
D
CP
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
OCTOBER 2008
DSC-2630/13
© 2006 Integrated Device Technology, Inc.
IDT74FCT377AT/CT/DT
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Max
–0.5 to +7
–0.5 to V
CC
+0.5
–65 to +150
–60 to +120
Unit
V
V
°C
mA
CE
O
0
D
0
D
1
O
1
O
2
D
2
D
3
O
3
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
O
7
D
7
D
6
O
6
O
5
D
5
D
4
O
4
CP
V
TERM
(2)
V
TERM
(3)
T
STG
I
OUT
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
Vcc by +0.5V unless otherwise noted.
2. Inputs and Vcc terminals only.
3. Output and I/O terminals only.
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
6
8
Max.
10
12
Unit
pF
pF
NOTE:
1. This parameter is measured at characterization but not tested.
SOIC/ QSOP
TOP VIEW
PIN DESCRIPTION
Pin Names
D
0
– D
7
CE
O
0
– O
7
CP
Data Inputs
Clock Enable (Active LOW)
Data Outputs
Clock Pulse Input
Description
FUNCTION TABLE
(1)
Inputs
Operating Mode
Load “1”
Load “0”
Hold
NOTE:
1. H =
h =
L =
l =
X =
↑
=
Outputs
D
h
l
X
X
O
H
L
No Change
No Change
CP
↑
↑
↑
H
CE
l
l
h
H
HIGH Voltage Level
HIGH Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition
LOW Voltage Level
LOW Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition
Don't Care
LOW-to-HIGH Clock Transition
2
IDT74FCT377AT/CT/DT
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial : T
A
= –40°C to +85°C, V
CC
= 5.0V ± 5%
Symbol
V
IH
V
IL
I
IH
I
IL
I
I
V
IK
I
OS
V
OH
V
OL
I
OFF
V
H
I
CC
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
(4)
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
CC
= Max.
V
CC
= Max., V
I
= V
CC
(Max.)
V
CC
= Min., I
N
= –18mA
V
CC
= Max.
(3)
, V
O
= GND
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
CC
= 0V, V
IN
or V
O
- 4.5V
—
V
CC
= Max.
V
IN
= GND or V
CC
I
OH
= –8mA
I
OH
= –12mA
I
OL
= 48mA
V
I
= 2.7V
V
I
= 0.5V
Min.
2
—
—
—
—
—
–60
2.4
2
—
—
—
—
Typ.
(2)
—
—
—
—
—
–0.7
–120
3.3
3
0.3
—
200
0.01
Max.
—
0.8
±1
±1
±1
–1.2
–225
—
—
0.5
±1
—
1
Unit
V
V
µA
µA
µA
V
mA
V
V
µA
mV
mA
Input LOW Current
(4)
Input HIGH Current
(4)
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
Output LOW Voltage
Input/Output Power Off
Leakage
(5)
Input Hysteresis
Quiescent Power
Supply Current
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. The test limit for this parameter is ±5µA at T
A
= -55°C.
5. This parameter is guaranted but not tested.
3
IDT74FCT377AT/CT/DT
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol
ΔI
CC
I
CCD
Parameter
Quiescent Power Supply
Current TTL Inputs HIGH
Dynamic Power Supply
Current
(4)
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max., Outputs Open
CE
= GND
One Input Toggling
50% Duty Cycle
V
CC
= Max., Outputs Open
f
CP
= 10MHz
CE
= GND
One Bit Toggling
f
i
= 5MHz
50% Duty Cycle
V
CC
= Max., Outputs Open
f
CP
= 10MHz, 50% Duty Cycle
CE
= GND
Eight Bits Toggling
f
i
= 2.5MHz
50% Duty Cycle
V
IN
= V
CC
V
IN
= GND
Test Conditions
(1)
Min.
—
—
Typ.
(2)
0.5
0.15
Max.
2
0.25
Unit
mA
mA/
MHz
I
C
Total Power Supply
Current
(6)
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
—
—
1.5
2
3.5
5.5
mA
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
—
—
3.8
6
7.3
(5)
16.3
(5)
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input; (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of
ΔI
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
ΔI
CC
D
H
N
T
+ I
CCD
(f
CP
/2+ f
i
N
i
)
I
CC
= Quiescent Current
ΔI
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Output Frequency
N
i
= Number of Outputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
t
PLH
t
PHL
t
SU
t
H
t
SU
t
H
t
W
Parameter
Propagation Delay
CP to Qx
Set-up Time HIGH or LOW
Dx to CP
Hold Time HIGH or LOW
Dx to CP
Set-up Time HIGH or LOW
CE
to CP
Hold Time HIGH or LOW
CE
to CP
CP Pulse Width HIGH or LOW
Condition
(1)
C
L
= 50pF
R
L
= 500Ω
74FCT377AT
Min.
(2)
Max.
2
7.2
2
1.5
3.5
1.5
8
—
—
—
—
—
74FCT377CT
Min.
(2)
Max.
2
5.2
2
1.5
3.5
1.5
6
—
—
—
—
—
74FCT377DT
Min.
(2)
Max.
2
4.4
2
1
3
0
3
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
4
IDT74FCT377AT/CT/DT
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
V
CC
500W
V
IN
Pulse
Generator
R
T
D.U.T
.
V
OUT
7.0V
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
All Other Tests
Switch
Closed
Open
50pF
C
L
500W
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
Octal Link
Test Circuits for All Outputs
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
t
SU
t
H
t
REM
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
t
W
HIGH-LOW-HIGH
PULSE
1.5V
1.5V
t
SU
t
H
Pulse Width
Octal Link
Octal Link
Set-Up, Hold, and Release Times
ENABLE
SAME PHASE
INPUT TRANSITION
t
PLH
OUTPUT
t
PLH
OPPOSITE PHASE
INPUT TRANSITION
t
PHL
t
PHL
3V
1.5V
0V
V
OH
1.5V
V
OL
3V
1.5V
0V
CONTROL
INPUT
t
PZL
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
t
PZH
SWITCH
OPEN
1.5V
0V
3.5V
1.5V
t
PHZ
DISABLE
3V
1.5V
0V
3.5V
0.3V
0.3V
V
OL
V
OH
0V
Octal Link
t
PLZ
Octal Link
Propagation Delay
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
