CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
Supply Current
Reference Voltage
Input Current
Output Current
Source
Sink
Output Buffer
At T
A
= 25
o
C, V
CC
= 10V, V
BIAS
= 3.75V, V
V
(Pin 8) = V
H
(Pin 10) = 6.0V, S
1
= A, S
2
= A,
See Test Circuit and Timing Diagrams
TEST PIN NO. SYMBOL
22
2, 4, 6
2, 4, 6
17,19, 21
I
CC
V
REF
I
I
l
OM
+
l
OM
-
17,19, 21
I
I
A
V
17,19, 21
g
M
V
OL
V
OH
l
OM
-
11
V
OL
V
OH
12
V
OL
V
OH
8
10
13
V
V
V
H
Measure at t
4
V
IN
= 7.2V, S
1
= B
V
BIAS
= 0.5V, Measure at t
6
, S
1
= B
V
BIAS
= 7.0V, Measure at t
6
, S
1
= B
V
OUT
= 6.5V, V
IN
At pins 16, 18, 20,
Measure at t
4
, S
1
= B
Measure at t
6
, V
IN
= 8mV
P-P
at 40kHz, S
1
= B
Measure at t
1
Measure at t
4
Measure at t
4
, S
2
= B
Measure at t
4
Measure at t
1
Measure at t
6
Measure at t
1
See Figure 3
See Figure 3
t
0
to t
2
, Note 2
t
0
to t
7
, Note 2
11
t
0
to t
3
, Note 2
t
0
to t
5
, Note 2
12
t
0
to t
5
, Note 2
t
0
to t
7
, Note 2
TEST CONDITIONS
MIN
-
5.6
-
-
0.8
-
0.97
50
TYP
-
6.0
-
-
-
-
-
-
MAX
65
6.4
250
-0.8
-
150
1.07
100
UNITS
mA
V
nA
mA
mA
nA
-
mS
Input Current
Voltage Gain
Transconductance
Auto Bias Pulse
Output Low
High
Current Sink
13
-
6.05
2.5
-
4.2
-
8.2
-
-
835
1270
899
1080
1080
1270
-
-
-
-
-
-
-
6.0
6.0
-
-
-
-
-
-
0.3
-
-
0.4
-
0.4
-
-
-
842
1275
905
1084
1084
1275
V
V
mA
V
V
V
V
V
V
µs
µs
µs
µs
µs
µs
Grid Pulse Output
Low
High
Program Pulse Output
Low
High
Vertical Input
Horizontal Input
Auto Bias Pulse Timing Start
Finish
Grid Pulse Timing
Start
Finish
Program Pulse Timing
Start
Finish
NOTE:
2. All time measurements are made from 50% point to 50% point.
8-57
CA3224E
Test Circuit
+10V
3.65K
1
V
IN1
2
22
B
21
S
1
3
0.047
µF
V
IN2
4
19
S
1
5
0.047
µF
V
IN3
6
17
S
1
CA3224E
7
VERTICAL
INPUT
0.047
µF
8
16
15
18
B
A
20
B
A
A
0.12µF
V
BIAS
Device Description and Operation
(See Figures 1, 2, 4 and 5)
During the vertical retrace interval, 13 horizontal sync pulses
are counted. On the 14th sync pulse the auto-bias pulse out-
put goes high. This is used to set the RGB drive of the com-
panion chroma/luma circuit to black level. The auto-bias pulse
stays high for 7 horizontal periods during the auto-bias cycle.
On the 15th horizontal sync pulse, the internal logic initiates
the setup interval. During the setup interval, the cathode cur-
rent is increased to a reference value (A in Figure 5) through
the action of the grid pulse. The cathode current causes a
voltage drop across R
S
. This voltage drop, together with the
program pulse output results in a reference voltage at V
S
(summing point) which causes capacitor C
1
to charge to a
voltage proportional to the reference cathode current. The
setup interval lasts for 3 horizontal periods.
On the 18th horizontal sync pulse the grid pulse output goes
high, which through the grid pulse amplifier/inverter, causes
the cathode current to decrease. The decrease in cathode
current results in a positive recovered voltage pulse with
respect to the setup reference level at the V
S
summing point.
The positive recovered voltage pulse is summed with a nega-
tive voltage pulse caused by the program pulse output going
low (cutting off Diode D
1
and switching in resistors R
1
and
R
2
). Any difference between the positive and negative pulses
is fed through capacitor C
1
to the transconductance amplifier.
The difference signal is amplified in the transconductance
amplifier and charges the hold capacitor C
2
, which, through
the buffer amplifier, adjusts the bias on the driver circuit.
Components R
S
, R
1
, and R
2
must be chosen such that the
program pulse and the recovered pulse just cancel at the
desired cathode cutoff level.
V
OUT1
3.65K
0.12µF
V
OUT2
3.65K
0.12µF
47µF
+
V
OUT3
9
14
+20V
3.32K
1.50K
1.0K
B
+10V
HORIZONTAL
INPUT
10
11
13
20K
12
S
2
A
1.5K
CHAN FREQ
1 IN COMP
2
3
HOLD
CHAN CHAN FREQ
CAPACITOR 1 OUT 2 IN COMP
21
20
4
5
HOLD
CAPACITOR
19
CHAN
2 OUT
18
CHAN FREQ
3 IN COMP
6
7
HOLD
CAPACITOR
17
CHAN
3 OUT
16
AMPLIFER
NO. 1
1
BUFFER
AMP
x1
AMPLIFER
NO. 2
1
g
M
BUFFER
AMP
x1
AMPLIFER
NO. 3
1
BUFFER
AMP
x1
-
+
g
M
2
3
-
+
2
-
+
g
M
2
3
3
V
REF
MODE
SWITCH
BIAS
LOGIC
1
GND
MODE SWITCH
1
2
3
9
GND
STATE
SET-UP
SENSE
OPEN
22
V
CC
15
V
REF
BYPASS
8
VERT
IN
10
HORIZ
IN
11
GRID
PULSE
OUT
12
PROG
PULSE
OUT
13
AUTO
BIAS
PULSE
OUT
14
AUTO
BIAS
LEVEL
ADJUST
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM
8-58
CA3224E
t
0
t
1
t
2
t
3
t
4
t
5
t
6
t
7
VERTICAL INPUT
(PIN 8)
HORIZONTAL INPUT
(PIN 10)
1
AUTO BIAS
PULSE OUTPUT
(PIN 13)
GRID PULSE OUTPUT
(PIN 11)
PROGRAM PULSE
OUTPUT
(PIN 12)
VERTICAL
BLANKING
2
3
12
13 14 15
16 17
18
19
20 21
22
23
MODE SWITCH
(SEE FIGURE 1)
OPEN
SET-UP
SENSE
OPEN
FIGURE 2. FUNCTIONAL TIMING DIAGRAMS
VERTICAL SIGNAL 0V
V
V
0.5ms
16.683ms
f
V
= 59.94Hz
HORIZONTAL SIGNAL
0V
12µs
V
H
f
H
= 15734.264Hz
63.55
µs
FIGURE 3. VERTICAL AND HORIZONTAL INPUT SIGNALS
8-59
CA3224E
+230V
12K
2.2K
R
G
B
+12V
Q
1
CATH
DRIVE
1
SG
2
0.047
3
C
C
G
IN
0.047
5
B
IN
0.047
7
12
+10V
TO B
CH
22
9
AUTO-BIAS PULSE
13
10
8
11
15
14
20K
AUTO BIAS
LEVEL ADJUST
HORIZONTAL
INPUT
VERTICAL
INPUT
6
17
CA224E
16
4
18
19
20
R
OUT
21
10K
Q
3
+
33µF
3.9K
+10V
1.5K
+
10µF
R
CHROMA/
LUMA
2.7K
CIRCUIT G
B
TO R
DRIVER
BIAS
5K
R
FB
160K
R
IN
R
S
560Ω
1%
SUMMING POINT
200Ω
V
S
0.12
C
1
R
2
62K
1%
TO R
CH
D
1
GRID PULSE
AMPLIFIER
INVERTER
+
C
2
10µF
G
OUT
G
IN
+
10µF
Q
2
BIAS
20K
+
B
OUT
47µF
TO B
DRIVER
-24V
PROGRAM
RGB TO
BLACK LEVEL
9.1K
2.7K
R
1
39K
1%
NOTE:
3. One of three identical driver circuits shown.
FIGURE 4. TYPICAL APPLICATION CIRCUIT
Electrostatic Protection
(Note)
I
CATHODE
(mA)
A
B
0
SET-UP
SENSE
V
CATHODE GRID
(V)
When correctly designed for ESD protection, SCRs can be
highly effective, enabling circuits to be protected to well in
excess of 4kV. The SCR ESD-EOS protection structures used
on each terminal of the CA3224E are shown schematically in
either Figures 6A or 6B. Although ESD-EOS protection is
included in the CA3224E, proper circuit board layout and
grounding techniques should be observed.
NOTE: For further information on CA3224E protection structures refer
to: AN7304, “Using SCRs as Transient Protection Structures in
Integrated Circuits”, by L.R. Avery. Harris AnswerFAX (407-724-7800)
EtherCAT（Ethernet for Control Automation Technology）是一种基于以太网的开发构架的实时工业现场总线通讯协议，EtherCAT是最快的工业以太网技术之一，同时它提供纳秒级精确同步。相对于设置了相同循环时间的其他总线系统，EtherCAT系统结构通常能减少25%-30%的CPU负载，EtherCAT的出现为系统的实时性能和拓扑的灵活性树立了新的标准。...[详细]
1. Introduction
Electronic scales are gradually replacing traditional measuring tools like springs and balances in everyday life, such as electronic price computing scales and electronic weigh...[详细]
电子竞赛
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
