v1.0
ProASIC3L Low-Power Flash FPGAs
with Flash*Freeze Technology
Features and Benefits
Low Power
• Dramatic Reduction in Dynamic and Static Power Savings
• 1.2 V / 1.5 V Core and I/O Voltage Support for Low Power
• Low Power Consumption in Flash*Freeze™ Mode Allows for
Instantaneous Entry to / Exit from Low-Power Flash*Freeze
Mode
• Supports Single-Voltage System Operation
• Low-Impedance Switches
®
High Capacity
• 250 k to 3 M System Gates
• Up to 504 kbits of True Dual-Port SRAM
• Up to 620 User I/Os
Reprogrammable Flash Technology
•
•
•
•
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
Live-at-Power-Up (LAPU) Level 0 Support
Single-Chip Solution
Retains Programmed Design when Powered Off
• Bank-Selectable I/O Voltages—up to 8 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and
LVCMOS 2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL, LVDS, BLVDS, and M-LVDS
• Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL
2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3
Class I and II (A3PE3000L only)
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold-Sparing I/Os Programmable
Output Slew Rate and Drive Strength
• Programmable Input Delay (A3PE3000 only)
• Schmitt Trigger Option on Single-Ended Inputs (A3PE3000L)
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the ProASIC
®
3L Family
(except PQ208)
Clock Conditioning Circuit (CCC) and PLL
• Six CCC Blocks, One with Integrated PLL (ProASIC3L) and All
with Integrated PLL (ProASIC3EL)
• Configurable
Phase
Shift, Multiply/Divide,
Delay
Capabilities, and External Feedback
• Wide Input Frequency Range 1.5 MHz to 250 MHz (1.2 V
systems) and 350 MHz (1.5 V systems))
High Performance
• 350 MHz (1.5 V systems) and 250 MHz (1.2 V systems) System
Performance
• 3.3 V, 66 MHz, 66-Bit PCI (1.5 V systems) and 66 MHz, 32-Bit
PCI (1.2 V systems)
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption via JTAG (IEEE 1532–compliant)
• FlashLock
®
to Secure FPGA Contents
SRAMs and FIFOs
• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,
and ×18 organizations available)
• True Dual-Port SRAM (except ×18)
• 24 SRAM and FIFO Configurations with Synchronous
Operation:
– 250 MHz: For 1.2 V systems
– 350 MHz: For 1.5 V systems
®
• ARM Cortex™-M1 Soft Processor Available with or without
Debug
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
• High-Performance, Low-Skew Global Network
• Architecture Supports Ultra-High Utilization
Advanced and Pro (Professional) I/Os
• 700 Mbps DDR, LVDS-Capable I/Os
• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Table 1-1 •
ProASIC3 Low-Power Product Family
ARM Processor Support in ProASIC3L FPGAs
ProASIC3L Devices
A3P250L
A3P600L
1
ARM Cortex-M1 Devices
M1A3P600L
System Gates
250 k
600 k
VersaTiles (D-flip-flops)
6,144
13,824
RAM kbits (1,024 bits)
36
108
4,608-Bit Blocks
8
24
FlashROM Bits
1k
1k
2
Secure (AES) ISP
Yes
Yes
3
Integrated PLL in CCCs
1
1
VersaNet Globals
18
18
I/O Banks
4
4
Maximum User I/Os
157
235
Package Pins
VQFP
VQ100
PQFP
PQ208
PQ208
FBGA
FG144, FG256
FG144, FG256, FG484
Notes:
1. Refer to the
Cortex-M1
product brief for more information.
2. AES is not available for ARM-enabled ProASIC3L devices.
3. For the A3PE3000L, the PQ208 package has six CCCs and two PLLs.
A3P1000L
M1A3P1000L
1M
24,576
144
32
1k
Yes
1
18
4
300
A3PE3000L
M1A3PE3000L
3M
75,264
504
112
1k
Yes
6
18
8
620
PQ208
3
FG324, FG484, FG896
PQ208
FG144, FG256, FG484
April 2008
© 2008 Actel Corporation
I
I/Os Per Package
1
ProASIC3L
Low-Power
Devices
ARM
Cortex-M1
Devices
A3P250L
3
A3P600L
A3P1000L
A3PE3000L
M1A3P600L
I/O Type
M1A3P1000L
M1A3PE3000L
Package
VQ100
PQ208
FG144
FG256
FG324
FG484
FG896
Notes:
Single-
Ended I/O
2
68
151
97
157
–
–
–
Differential
I/O Pairs
13
34
24
38
–
–
–
Single-
Ended I/O
2
Differential
I/O Pairs
–
Single-
Ended I/O
2
–
154
97
177
–
300
–
Differential
I/O Pairs
–
35
25
44
–
74
–
Single-
Ended I/O
2
–
147
Differential
I/O Pairs
–
65
154
97
177
–
235
–
35
25
43
–
60
–
–
221
341
620
–
110
168
300
1. When considering migrating your design to a lower- or higher-density device, refer to the packaging section of the
datasheet to ensure you are complying with design and board migration requirements.
2. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
3. For A3P250L devices, the maximum number of LVPECL pairs in east and west banks cannot exceed 15.
4. FG256 and FG484 are footprint-compatible packages.
5. "G" indicates RoHS-compliant packages. Refer to
"ProASIC3L Ordering Information" on page III
for the location of the
"G" in the part number.
6. For A3PE3000L devices, the usage of certain I/O standards is limited as follows:
– SSTL3(I) and (II): up to 40 I/Os per north or south bank
– LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank
– SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank
7. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not as a regular I/O, the number of single-
ended user I/Os available is reduced by one.
II
v1.0
ProASIC3L Low-Power Flash FPGAs
ProASIC3L Ordering Information
A3P1000L
_
1
FG
G
144
I
Application (Temperature Range)
Blank =
Commercial
(0°C to +70°C Ambient Temperature)
I = Industrial (
–
40°C to +85°C Ambient Temperature)
Package Lead
Count
Lead-Free Packaging
Blank =
Standard
Packaging
G=
RoHS-Compliant (Green) Packaging
Package Type
VQ = Very Thin Quad Flat Pack (0.5 mm pitch)
PQ = Plastic Quad Flat Pack (0.5 mm pitch)
FG = Fine Pitch Ball
Grid
Array (1.0 mm pitch)
Speed Grade
Blank =
Standard
1 = 15% Faster than
Standard
Part Number
ProASIC3L Devices
A3P250L = 250,000
System Gates
A3P600L =
600,000 System Gates
A3P1000L = 1,000,000
System Gates
A3PE3000L = 3,000,000
System Gates
ProASIC3L Devices with Cortex-M1
M1A3P600L =
600,000 System Gates
M1A3P1000L = 1,000,000
System Gates
M1A3PE3000L = 3,000,000
System Gates
v1.0
III
Temperature Grade Offerings
Package
ARM Cortex-M1 Devices
VQ100
PQ208
FG144
FG256
FG324
FG484
FG896
Notes:
1. C = Commercial temperature range: 0°C to 70°C ambient temperature.
2. I = Industrial temperature range: –40°C to 85°C ambient temperature.
C, I
C, I
C, I
C, I
–
–
–
A3P250L
A3P600L
M1A3P600L
–
C, I
C, I
C, I
–
C, I
–
A3P1000L
M1A3P1000L
–
C, I
C, I
C, I
–
C, I
–
C, I
C, I
C, I
C, I
A3P3000L
M1A3PE3000L
Speed Grade and Temperature Grade Matrix
Temperature Grade
C
1
I
2
Notes:
1. C = Commercial temperature range: 0°C to 70°C ambient temperature.
2. I = Industrial temperature range: –40°C to 85°C ambient temperature.
Contact your local Actel representative for device availability:
http://www.actel.com/contact/default.aspx.
Std.
–1
✓
✓
✓
✓
IV
v1.0
1 – ProASIC3L Device Family Overview
General Description
The ProASIC3L family of Actel flash FPGAs dramatically reduces dynamic power consumption by
40% and static power by 50%. These power savings are coupled with performance, density, true
single-chip, 1.2 V / 1.5 V core and I/O operation, reprogrammability, and advanced features.
Using Actel's proven Flash*Freeze technology enables users to shut off dynamic power
instantaneously and switch the device to static mode without the need to switch off clocks or
power supplies while retaining internal states of the device. This greatly simplifies power
management on a board done through I/Os and clocks. In addition, optimized software tools using
power-driven layout provide instant push-button power reduction.
Nonvolatile flash technology gives ProASIC3L devices the advantage of being a secure, low-power,
single-chip solution that is live at power-up (LAPU). ProASIC3L offers dramatic dynamic power
savings giving the FPGA users flexibility to combine low power with high performance.
These features enable designers to create high-density systems using existing ASIC or FPGA design
flows and tools.
ProASIC3L devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well
as clock conditioning circuitry (CCC) based on an integrated phase-locked loop (PLL). ProASIC3L
devices support devices from 250 k system gates to 3 million system gates with up to 504 kbits of
true dual-port SRAM and 620 user I/Os.
M1 ProASIC3L devices support the high-performance, 32-bit Cortex-M1 processor developed by
ARM for implementation in FPGAs. ARM Cortex-M1 is a soft processor that is fully implemented in
the FPGA fabric. It has a three-stage pipeline that offers a good balance between low-power
consumption and speed when implemented in an M1 ProASIC3L device. The processor runs the
ARMv6-M instruction set, has a configurable nested interrupt controller, and can be implemented
with or without the debug block. ARM Cortex-M1 is available for free from Actel for use in M1
ProASIC3L FPGAs.
The ARM-enabled devices have Actel ordering numbers that begin with M1 and do not support
AES decryption.
Flash*Freeze Technology
The ProASIC3L devices offer Actel's proven Flash*Freeze technology, which allows instantaneous
switching from an active state to a static state. ProASIC3L devices do not need additional
components to turn off I/Os or clocks while retaining the design information, SRAM content, and
registers. Flash*Freeze technology is combined with in-system programmability, which enables
users to quickly and easily upgrade and update their designs in the final stages of manufacturing
or in the field. The ability of ProASIC3L devices to support a 1.2 V core voltage allows for an even
greater reduction in power consumption, which enables low total system power.
When the ProASIC3L device enters Flash*Freeze mode, the device automatically shuts off the clocks
and inputs to the FPGA core; when the device exits Flash*Freeze mode, all activity resumes and
data is retained.
The availability of low-power modes, combined with a reprogrammable, single-chip, single-voltage
solution, make ProASIC3L devices suitable for low-power data transfer and manipulation in
portable media, secure communications, radio applications as well as high performance portable,
industrial, test, scientific, and medical applications.
v1.0
1-1
PCB设计
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