Intel
®
82576 Gigabit Ethernet
Controller Datasheet
LAN Access Division (LAD)
PRODUCT FEATURES
External Interfaces
PCIe* v2.0 (2.5 GT/s) x4/x2/x1; called PCIe in this
document
MDI (Copper) standard IEEE 802.3 Ethernet interface
for 1000BASE-T, 100BASE-TX, and 10BASE-T
applications (802.3, 802.3u, and 802.3ab)
Serializer-Deserializer (SERDES) to support 1000Base-
SX/X/LX (optical fiber) for Gigabit backplane
applications.
SGMII for SFP/external PHY connections
NC-SI (Type C) or SMBus for Manageability connection
to BMC.
IEEE 1149.1 JTAG
Intel® I/O Acceleration Technology
Stateless offloads (Header split, RSS)
Intel® QuickData (DCA - Direct Cache Access)
Virtualization Ready
Next Generation VMDq support (8 VMs)
PCI-SIG Single Root I/O Virtualization (Direct
assignment)
Queues per port: 16 TX queues and 16 RX queues
Full-Spectrum Security
IPsec (256 SA’s) in 82576EB; IPsec not present in
82576NS [Non-Security]
MACSec
Additional Product Details
25mm x 25mm Package
Power 2.8W (max)
Support for PCI 3.0 Vital Product Data
Memories Parity or ECC Protection
IPMI MC Pass-thru; Multi-drop NC-SI
802.1AS draft standard implementation
Layout Compatible with 82575
320961-015EN
Revision: 2.61
December 2010
Intel
®
82576 GbE Controller — Legal
Legal
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*Other names and brands may be claimed as the property of others.
Copyright © 2007, 2008, 2009, 2010; Intel Corporation. All Rights Reserved.
Intel
®
82576 GbE Controller
Datasheet
2
320961-015EN
Revision: 2.61
December 2010
Revisions — Intel
®
82576 GbE Controller
Revisions
Revision
0.5
1.0
1.9
2.0
2.1
2.2
Date
6/2007
11/2007
5/2008
6/2008
7/2008
11/2008
Comments
Initial availability.
Updates and corrections.
PRQ release.
SRA release.
Maintenance update. Added checklist chapter.
Maintenance update.
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ected device ID reference to 0x10C9.
Section 3.3.1.7; Section 12.3.2.2.1
- EEPROM-less information updated; stronger
statements about EEPROM-less design.
Table 3-17
- Device ID corrected.
GIO_PWR_GOOD updated to PERST# throughout.
Section 6.1
- More PXE information documented. Entire section updated. See PXE
listings on EEPROM map. Also, links added for entire EEPROM reference map.
Section 7.10.3.5.1, Section 7.10.3.5.2-
Notes added after VFRE filtering
paragraphs in numbered list.
Section 8.8.7, Section 8.8.8, Section 8.8.9, Section 8.8.10
- The ICR, ICS, IMS,
IMC registers were corrected. See bit 3 in each.
Chapter 10.0, System Manageability
updated; organization changed; some
additional information provided.
Section 10.6.2.12
- Bit description in table updated (to 0x21).
Table 10-10
- IPV4 and IPV6 filter parameter information corrected.
Table 10-33
- List of supported commands has been updated.
Table 11.4.2.1
- Current consumption data updated. See bold text in table. Also,
see power data in summary on title page.
Table 12-2
- Additional magnetics recommendation added.
Section 6.2.18
- Bit 15 information updated; Enable WAKE# Assertion.
Jumbo frame size consistently indicated at 9500 bytes (max).
SKU 82576NS documented. The IPsec function is present in the 82576EB SKU.
IPsec is not present in the 82576NS SKU. This is indicated throughout the
document.
Section 3.3.4.2, Flash Write Control
- Typing correction.
Note that attempts to write
to the Flash device when writes are disabled (EEC.FWE=01b) should not be
attempted.
Section 3.4.2, Software Watchdog
- Updated. Edited to describe the software
interrupt (ICR[26]) and to reduce confusion.
Section 3.5.6.5.1, Setting the 82576 to External PHY loopback Mode
- Text added
at the end of the section for clarity:
The above procedure puts the device in PHY
loopback mode. After using the procedure, wait for link to become up. Once PHY
register 1 bit 2 is set (this can take up to 750ms), transmit and receive normally. If
you are unable to get link after 750ms, reset the PHY using CTRL.PHY_RST and
then repeat the above procedure. When exiting External PHY loopback mode, a full
PHY reset must be done. Use CTRL.PHY_RST.
2.3
2.4
12/2008
4/1/2009
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320961-015EN
Revision: 2.61
December 2010
Intel
®
82576 GbE Controller
Datasheet
3
Intel
®
82576 GbE Controller — Revisions
Revision
Date
Comments
•
Section 4.4, Device Disable
- The following phrase in the section has been changed:
The EEPROM "Power Down Enable" bit (Section
6.2.7)
enables device disable mode
(hardware default is that the mode is disabled).
Table 4-5, 82576 Reset Effects - Per Function Resets
- Table updated. See the
entries on PCI Configuration registers and the associated footnotes.
Section 4.2.1.6.3, VF Software Reset
- Replaced VFCTRL with VTCTRL (corrects a
typo). Added information that indicates what happens when VTCTRL.RST is set.
Setting VTCTRL.RST resets interrupts and queue enable bits. Other VF registers are
not reset.
Section 5.0, Power Management
updated for clarity.
Section 6.10.7.1, iSCSI Module Structure
- Description of structure updated.
Multiple errors were corrected
Section 7.1.3.1, Host Buffers
- Text added.
For advanced descriptor usage, the
SRRCTL.BSIZEHEADER field is used to define the size of the buffers allocated to
headers. The maximum buffer size supported is 960 bytes..
Section 8.2.4, MDI Control Register - MDIC (0x00020; R/W)
- Description of bit 31
corrected.
Section 8.10.2, Split and Replication Receive Control - SRRCTL (0x0C00C + 0x40*n
[n=0...15]; R/W).
Maximum 960 bytes now indicated for SRRCTL.BSIZEHEADER.
Section 10.4.4.3, RMCP Filtering
- Title of section updated.
Section 10.5.10.1.4, Force TCO Command
and
Section 10.6.2.13.1, Perform Intel
TCO Reset Command (Intel Command 0x22)
- Added description of RESET_MGMT
bit.
Section 10.5.12, Example Configuration Steps
- Added pseudocode describing the
setup of common filtering configurations.
Table 10-35, Command Summary
- Commands added, see:
0x02 0x67/68 Set EtherType Filter/Packet Add. Ext. Filter
0x03 0x67/68 Get EtherType Filter/Packet Add. Ext. Filter
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Section 10.5.10.2.1, Receive TCO LAN Packet Transaction.
Description of packet
structure added.
Section 10.6.2.6.19, Set Intel Filters - Packet Addition Extended Decision Filter
Command (Intel Command 0x02, Filter parameter 0x68).
Text in section updated:
Extended decision filter index range adjusted to 0..4.
Table 11-5, Current Consumption Details
- Added SGMII note to table.
(3) To
estimate power for SGMII mode, use the SerDes mode power numbers provided.
Table 11-22, Package Height
- Table added. Provides a summary of package height
information.
Section 7.1.4, Legacy Receive Descriptor Format
and
Section 7.2.2, Transmit
Descriptors.
Recommendation regarding legacy descriptors changed to ‘must not be
used’ from ‘should not be used.’
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2.41
4/8/2009
5/5/2009
2.42
2.43
7/5/2009
10/2/2009
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Internal release for test and review.
MACSec capability exposed. You must have a MACSec-ready switch in order to com-
plete the ecosystem and make use of MACSec functionality.
Maintenance issues addressed:
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Section 7.2.4.7.2, TCP/IP/UDP Headers for the Subsequent Frames
and
Section
7.2.4.7.3, TCP/IP/UDP Headers for the Last Frame
updated to document UDP fields.
Section 7.3.3.2, Interrupt Moderation
and
Section 8.8.12, Interrupt Throttle - EITR
(0x01680 + 4*n [n = 0...24]; R/W)
updated to correct minor issues; redundant
data removed.
Table 7-9, VLAN Tag Field Layout (for 802.1q Packet)
- Note added to table that
clarifies usage:
• NOTE: This table is relevant only if VMVIR.VLANA = 00b (use descriptor
command) for the queue.
•
Intel
®
82576 GbE Controller
Datasheet
4
320961-015EN
Revision: 2.61
December 2010
Revisions — Intel
®
82576 GbE Controller
Revision
Date
Comments
•
Section 7.10.3.2.1, Filtering Capabilities
- Typo corrected. In bullet, VM changed to
VF. Below:
• Promiscuous multicast & enable broadcast per VF.
Section 7.10.3.8, Offloads
- Note added; text below:
• NOTE: VLAN strip offload is determined based only on the L2 MAC address. In
order to make sure VLAN strip offload is correctly applied, all packets should be
initially forwarded using one of the L2 MAC address filters (RAH/RAL, UTA,
MTA, VMOLR.BAM, VMOLR.MPE.
Two table titles corrected. Could have caused confusion. Minor edits also made to
field descriptions.
•
Table 7-35, TCP/IP or UDP/IP Packet Format Sent by Host
•
Table 7-36, TCP/IP or UDP/IP Packet Format Sent by 82576
Section 8.10.7, Receive Descriptor Ring Length - RDLEN (0x0C008 + 0x40*n
[n=0...15]; R/W)
- Description updated. LEN text added: The maximum allowed
value is 0x80000 (32K descriptors).
Section 8.12.2, Transmit Control Extended - TCTL_EXT (0x0404; R/W)
- Default
value of COLD corrected (0x42) in text description.
Section 10.5.10.1.4, Force TCO Command
- Clarification note added to table. See
below:
• NOTE: Before initiating a Firmware reset command, one should disable TCO
receive via Receive Enable Command -- setting RCV_EN to 0 -- and wait for 200
milliseconds before initiating Firmware Reset command. In addition, the
MCshould not transmit during this period.
Section 10.5.10.2.1, Receive TCO LAN Packet Transaction
- Receive TCO packet
format table updated; numerous changes. For clarity.
Section 10.7.10, Read Fail-Over Configuration Host Command
- Both tables in
section updated.
•
Table 10-49, Commands to Read the Fail-Over Configuration Register
- Last row
in table deleted; was incorrect.
•
Table 10-50, States Returned
- Description column (byte 1) updated.
Description was confusing.
Section 10.5.12.3.1, Example 3 - Pseudo Code
- Pseudo Code, step 5: MAC Address
Filtering is bit 0, not bit 1. Also the MDEF value is 00000009 and not 00000040.
Section 10.5.12.4.1, Example 4 - Pseudo Code
- Step 5: Configure MDEF[0], MDEF
value is 0000004 and not 00000040.
Section 9.6.4.3, PCIe SR-IOV Control Register (0x168; RW);
Bit 4; ARI Capable
Hierarchy. Text updated.
Section 10.0, System Manageability;
More information on MACSec parameters
provided. See
Section 10.5.10.1.6, Update MACSec Parameters
and
Section 10.8,
MACSec and Manageability
in particular.
Section 10.5.10.1.3, Receive Enable Command; Section 10.5.10.2.5, Read
Management Receive Filter Parameters.
Bit order expression corrected in two
tables. See bold text.
References to BMC changed to MC if the reference is not programmatic.
Section 3.3.1.6, EEPROM Recovery.
Section now exposed in the datasheet.
Section 8.10.8, Receive Descriptor Head - RDH (0x0C010 + 0x40*n [n=0...15];
RO)
and
Section 8.12.11, Transmit Descriptor Head - TDH (0x0E010 + 0x40*n
[n=0...15]; RO).
Both registers indicated RW incorrectly. Changed to RO.
Table 10-33, Supported NC-SI Commands
and
Table 10-34, Optional NC-SI
Features Support.
List of supported commands/functions updated to correct an
error in our support statements. See bold text in both tables.
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2.44
10/14/2009
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2.45
10/30/2009
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320961-015EN
Revision: 2.61
December 2010
Intel
®
82576 GbE Controller
Datasheet
5
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