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TMS320C1x
DIGITAL SIGNAL PROCESSORS
SPRS009C – JANUARY 1987 – REVISED JULY 1991
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Performance Up to 8.77 MIPs
All TMS320C1x Devices are Object Code
Compatible
144/256-Word On-Chip Data RAM
1.5K/4K/8K-Word On-Chip Program ROM
4K-Word On-Chip Program EPROM
(TMS320E14/P14/E15/P15/E17/P17)
One-Time Programmable (OTP)
Versions Available (TMS320P14/P15/P17)
EPROM Code Protection for Copyright
Security
4K / 64K-Word Total External Memory at
Full Speed
32-Bit ALU/Accumulator
16
×
16-Bit Multiplier With a 32-Bit Product
0 to 16-Bit Barrel Shifter
Eight Input/Output Channels
Dual-Channel Serial Port
Simple Memory and I/O Interface
5-V and 3.3-V Versions Available
(TMS320LC15/LC17)
•
•
•
•
Commercial and Military Versions Available
Operating Free-Air Temperature
. . . 0°C to 70°C
Packaging: DIP, PLCC, Quad Flatpack, and
CER-QUAD
CMOS Technology:
Device
Cycle Time
— TMS320C10 . . . . . . . . . . . . . . . . . . . 200-ns
— TMS320C10-14 . . . . . . . . . . . . . . . . 280-ns
— TMS320C10-25 . . . . . . . . . . . . . . . . 160-ns
— TMS320C14 . . . . . . . . . . . . . . . . . . . 160-ns
— TMS320E14 . . . . . . . . . . . . . . . . . . . 160-ns
— TMS320P14 . . . . . . . . . . . . . . . . . . . 160-ns
— TMS320C15 . . . . . . . . . . . . . . . . . . . 200-ns
— TMS320C15-25 . . . . . . . . . . . . . . . . 160-ns
— TMS320E15 . . . . . . . . . . . . . . . . . . . 200-ns
— TMS320E15-25 . . . . . . . . . . . . . . . . 160-ns
— TMS320LC15 . . . . . . . . . . . . . . . . . . 250-ns
— TMS320P15 . . . . . . . . . . . . . . . . . . . 200-ns
— TMS320C16 . . . . . . . . . . . . . . . . . . . 114-ns
— TMS320C17 . . . . . . . . . . . . . . . . . . . 200-ns
— TMS320E17 . . . . . . . . . . . . . . . . . . . 200-ns
— TMS320LC17 . . . . . . . . . . . . . . . . . . 278-ns
— TMS320P17 . . . . . . . . . . . . . . . . . . . 200-ns
introduction
The TMS32010 digital signal processor (DSP), introduced in 1983, was the first DSP in the TMS320 family. From
it has evolved this TMS320C1x generation of 16-bit DSPs. All
′C1x
DSPs are object code compatible with the
TMS32010 DSP. The
′C1x
DSPs combine the flexibility of a high-speed controller with the numerical capability
of an array processor, thereby offering an inexpensive alternative to multichip bit-slice processors. The highly
paralleled architecture and efficient instruction set provide speed and flexibility to produce a CMOS
microprocessor generation capable of executing up to 8.77 MIPS (million instructions per second) (′C16). These
′C1x
devices utilize a modified Harvard architecture to optimize speed and flexibility, implementing functions in
hardware that other processors implement through microcode or software.
The
′C1x
generation’s powerful instruction set, inherent flexibility, high-speed number-handling capabilities,
reduced power consumption, and innovative architecture have made these cost-effective DSPs the ideal
solution for many telecommunications, computer, commercial, industrial, and military applications.
This data sheet provides detailed design documentation for the
′C1x
DSPs. It facilitates the selection of devices
best suited for various user applications by providing specifications and special features for each
′C1x
DSP.
This data sheet is arranged as follows: introduction, quick reference table of device parameters and packages,
summary overview of each device, architecture overview, and the
′C1x
device instruction set summary. These
are followed by data sheets for each
′C1x
device providing available package styles, terminal function tables,
block diagrams, and electrical and timing parameters. An index is provided to facilitate data sheet usage.
PRODUCTION DATA information is current as of
publication date. Products conform to specifications
per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 1443
Copyright
©
1991, Texas Instruments Incorporated
•
HOUSTON, TEXAS 77001
1
TMS320C1x
DIGITAL SIGNAL PROCESSORS
SPRS009C – JANUARY 1987 – REVISED JULY 1991
Table 1 provides an overview of
′C1x
processors with comparisons of memory, I/O, cycle timing, military support,
and package types. For specific availability, contact the nearest TI Field Sales Office.
Table 1. TMS320C1x Device Overview
DEVICE
TMS320C10 (2)
TMS320C10-14
TMS320C10-25
TMS320C14 (3)
TMS320E14 (3)
TMS320P14†
TMS320C15 (3)
TMS320C15-25
TMS320E15 (3)
TMS320E15-25
TMS320LC15
TMS320P15†
TMS320C16
TMS320C17
TMS320E17 (5)
TMS320LC17 (5)
TMS320P17 (5)†
MEMORY
RAM
144
144
144
256
256
256
256
256
256
256
256
256
256
256
256
256
256
ROM
1.5K
1.5K
1.5K
4K
—
—
4K
4K
—
—
4K
—
8K
4K
—
4K
—
EPROM
—
—
—
—
4K
4K
—
—
4K
4K
—
4K
—
—
4K
—
4K
PROG.
4K
4K
4K
4K
4K
4K
4K
4K
4K
4K
4K
4K
64K
—
—
—
—
SERIAL
—
—
—
1
1
1
—
—
—
—
—
—
—
2
2
2
2
I/O
PARALLEL
8
×
16
8
×
16
8
×
16
7
×
16 (4)
7
×
16 (4)
7
×
16 (4)
8
×
16
8
×
16
8
×
16
8
×
16
8
×
16
8
×
16
8
×
16
6
×
16 (5)
6
×
16 (5)
6
×
16 (5)
6
×
16 (5)
CYCLE
(ns)
200
280
160
160
160
160
200
160
200
160
250
200
114
200
200
278
200
DIP
40
40
40
—
—
—
40
40
40
40
40
40
—
40
40
40
40
PACKAGE (1)
PLCC
44
44
44
68
—
68
44
44
—
—
44
44
—
44
—
44
44
CER-QUAD
—
—
—
—
68 CER
—
—
—
44 CER
44 CER
—
—
64 QFP
—
44 CER
—
† One-time programmable (OTP) device is in a windowless plastic package and cannot be erased.
NOTES: 1. DIP = dual in-line package. PLCC = plastic-leaded chip carrier. CER = ceramic-leaded chip carrier. QFP = plastic quad flat pack.
2. Military version available.
3. Military versions planned; contact nearest TI Field Sales Office for availability.
4. On-chip 16-bit I/O, four capture inputs, and six compare outputs are available.
5. On-chip 16-bit coprocessor interface is optional by pin selection.
2
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
TMS320C1x
DIGITAL SIGNAL PROCESSORS
SPRS009C – JANUARY 1987 – REVISED JULY 1991
description
TMS320C10
The
′C10
provides the core CPU used in all other
′C1x
devices. Its microprocessor operates at 5 MIPS. It
provides a parallel I/O of 8
×
16 bits. Three versions with cycle times of 160, 200, and 280 ns are available as
illustrated in Table 1. The
′C10
versions are offered in plastic 40-pin DIP or a 44-lead PLCC packages.
TMS320C14/E14/P14
The
′C14/E14/P14
devices, using the
′C10
core CPU, offer expanded on-chip RAM, and ROM or EPROM
(′E14/P14), 16 pins of bit selectable parallel I/O, an I/O mapped asynchronous serial port, four 16-bit timers, and
external/internal interrupts. The
′C14
devices can provide for microcomputer/microprocessor operating modes.
Three versions with cycle times of 160-ns are available as illustrated in Table 1. These devices are offered in
68-pin plastic PLCC or ceramic CER-QUAD packages.
TMS320C15/E15/P15
The
′C15/E15/P15
devices are a version of the
′C10,
offering expanded on-chip RAM, and ROM or EPROM
(′E15/P15). The
′P15
is a one-time programmable (OTP), windowless EPROM version. These devices can
operate in the microcomputer or microprocessor modes. Five versions are available with cycle times of 160 to
200 ns (see Table 1). These devices are offered in 40-pin DIP, 44-pin PLCC, or 44-pin ceramic packages.
TMS320LC15
The
′LC15
is a low-power version of the
′C15,
utilizing a V
DD
of only 3.3-V. This feature results in a 2.3: 1 power
requirement reduction over the typical 5-V
′C1x
device. It operates at a cycle time of 250 ns. The device is offered
in 40-pin DIP or 44-lead PLCC packages.
TMS320C16
The
′C16
offers on-chip RAM of 256-words, an expanded program memory of 64K-words, and a fast instruction
cycle time of 114 ns (8.77 MIPS). It is offered in a 64-pin quad flat-pack package.
TMS320C17/E17/P17
The
′C17/E17/P17
versions consist of five major functional units: the
′C15
microcomputer, a system control
register, a full-duplex dual channel serial port,
µ-law/A-law
companding hardware, and a coprocessor port. The
dual-channel serial port is capable of full-duplex serial communication and offers direct interface to two
combo-codecs. The hardware companding logic can operate in either
µ-law
or A-law format with either
sign-magnitude or twos complement numbers in either serial or parallel modes. The coprocessor port allows
the
′C17/E17/P17
to act as a slave microcomputer or as a master to a peripheral microcomputer.
The
′P17
utilizes a one-time programmable (OTP) windowless EPROM version of the
′E17.
TMS320LC17
The
′LC17
is a low-power version of the
′C17,
utilizing a V
DD
of only 3.3-V. This feature results in a
2.3: 1 power requirement reduction over the typical 5-V
′C1x
device. It operates at a cycle time of 278 ns.
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
3
TMS320C1x
DIGITAL SIGNAL PROCESSORS
SPRS009C – JANUARY 1987 – REVISED JULY 1991
TMS320C10/C15/LC15/P15
N/JD Packages
(Top View)
A1/PA1
A0/PA0
MC/MP
RS
INT
CLKOUT
X1
X2/CLKIN
BIO
VSS
D8
D9
D10
D11
D12
D13
D14
D15
D7
D6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A2/PA2
A3
A4
A5
A6
A7
A8
MEN
DEN
WE
VCC
A9
A10
A11
D0
D1
D2
D3
D4
D5
TMS320C17/E17/LC17/P17
N/JD Packages
(Top View)
PA1/RBLE
PA0/HI/LO
MC
RS
EXINT
CLKOUT
X1
X2/CLKIN
BIO
VSS
D8/LD8
D9/LD9
D10/Ld10
D11/LD11
D12/LD12
D13/LD13
D14/LD14
D15/LD15
D7/LD7
D6/LD6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PA2/TBLF
FSR
FSX
FR
DX1
DX0
SCLK
DR1
DEN/RD
WE/WR
VCC
DR0
XF
MC/PM
D0/LD0
D1/LD1
D2/LD2
D3/LD3
D4/LD4
D5/LD5
TMS320C10/C15/E15/LC15/P15
FN/FZ Packages
(Top View)
INT
RS
MC/MP
A0/PA0
A1/PA1
V CC
A2/PA2
A3
A4
A5
A6
6 5 4 3 2 1 44 43 42 41 40
CLKOUT
X1
X2/CLKIN
BIO
NC
VSS
D8
D9
D10
D11
D12
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28
V CC
D13
D14
D15
D7
D6
D5
D4
D3
D2
V CC
39
38
37
36
35
34
33
32
31
30
29
A7
A8
MEN
DEN
WE
VCC
A9
A10
A11
D0
D1
A9
CMP0
CMP1
A10
A11
VCC2
VSS2
CMP2
CMP3
CAP0
CAP1
AMP4/CAP2/FSR
CMP5/CAP3/FSX
D0
D1
D2
D3
TMS320C14/E14/P14
FN/FZ Packages
(Top View)
TMS320C16
PG Package
(Top View)
BIO
INT
MC/MP
V SS
V DD
V DD
V DD
V DD
MEN
NC
IOEN
MWE
IOWE
64636261605958575655545352
NC
RS
X1
X2/CLKIN
VSS
VSS
VSS
VSS
CLKOUT
D15
D14
NC
D13
D12
D11
D10
D9
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20212223242526272829303132
D8
D7
D6
D5
NC
D4
VDD
D3
D2
NC
D1
D0
A15
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
NC
NC
A0/PA0
A1/PA1
A2/PA2
A3
A4
A5
A6
VSS
A7
A8
A9
A10
A11
A12
A13
A14
NC
D4
D5
D6
D7
IOP0
IOP1
IOP2
IOP3
IOP4
IOP5
D8
D9
RXD/DATA
TXD/CLK
D10
IOP6
IOP7
TCLK/CLKR
TCLK2/CLKX
A8
A7
A6
WE
REN
RS
INT
CLKOUT
A5
A4
NMI/MC/MP
WDT
CLKIN
A3
A2
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
60
10
59
11
58
12
57
13
56
14
55
15
54
16
53
17
52
18
51
19
50
20
49
21
48
22
47
23
46
24
45
25
44
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
A1
A0
IOP15
IOP14
IOP13
IOP12
VCC1
VSS1
D15
D14
IOP11
IOP10
D13
D12
IOP9
IOP8
D11
TMS320C17/E17
FN/FZ Packages
(Top View)
EXINT
RS
MC
PAO/HI/LO
PA1/RBLE
VSS
PA2/TBLF
FSR
FSX
FR
DX1
6 5 4 3 2 1 44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
18 19 20 21 22 23 24 25 26 27 28
VSS
D13/LD13
D14/LD14
D15/LD15
D7/LD7
D6/LD6
D5/LD5
D4/LD4
D3/LD3
D2/LD2
D1/LD1
CLKOUT
X1
X2/CLKIN
BIO
NC
VSS
D8
D9
D10
D11
D12
7
8
9
10
11
12
13
14
15
16
17
DX0
SCLK
DR1
DEN/RD
WE/WR
VCC
DR0
XF
MC/PM
D0/LD0
VSS
4
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
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