INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4046A
Phase-locked-loop with VCO
Product specification
Supersedes data of September 1993
File under Integrated Circuits, IC06
1997 Nov 25
Philips Semiconductors
Product specification
Phase-locked-loop with VCO
FEATURES
•
Low power consumption
•
Centre frequency of up to 17 MHz (typ.) at V
CC
= 4.5 V
•
Choice of three phase comparators: EXCLUSIVE-OR;
edge-triggered JK flip-flop;
edge-triggered RS flip-flop
•
Excellent VCO frequency linearity
•
VCO-inhibit control for ON/OFF keying and for low
standby power consumption
•
Minimal frequency drift
•
Operating power supply voltage range:
VCO section 3.0 to 6.0 V
digital section 2.0 to 6.0 V
•
Zero voltage offset due to op-amp buffering
•
Output capability: standard
•
I
CC
category: MSI.
GENERAL DESCRIPTION
Phase comparators
The 74HC/HCT4046A are high-speed Si-gate CMOS
devices and are pin compatible with the “4046” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4046A are phase-locked-loop circuits that
comprise a linear voltage-controlled oscillator (VCO) and
three different phase comparators (PC1, PC2 and PC3)
with a common signal input amplifier and a common
comparator input.
The signal input can be directly coupled to large voltage
signals, or indirectly coupled (with a series capacitor) to
small voltage signals. A self-bias input circuit keeps small
voltage signals within the linear region of the input
amplifiers. With a passive low-pass filter, the “4046A”
forms a second-order loop PLL. The excellent VCO
linearity is achieved by the use of linear op-amp
techniques.
The VCO requires one external capacitor C1 (between
C1
A
and C1
B
) and one external resistor R1 (between
R
1
and GND) or two external resistors R1 and R2
(between R
1
and GND, and R
2
and GND). Resistor R1
and capacitor C1 determine the frequency range of the
VCO. Resistor R2 enables the VCO to have a frequency
offset if required.
The high input impedance of the VCO simplifies the design
of low-pass filters by giving the designer a wide choice of
resistor/capacitor ranges. In order not to load the low-pass
filter, a demodulator output of the VCO input voltage is
1997 Nov 25
2
74HC/HCT4046A
provided at pin 10 (DEM
OUT
). In contrast to conventional
techniques where the DEM
OUT
voltage is one threshold
voltage lower than the VCO input voltage, here the
DEM
OUT
voltage equals that of the VCO input. If
DEM
OUT
is used, a load resistor (R
S
) should be connected
from DEM
OUT
to GND; if unused, DEM
OUT
should be left
open. The VCO output (VCO
OUT
) can be connected
directly to the comparator input (COMP
IN
), or connected
via a frequency-divider. The VCO output signal has a duty
factor of 50% (maximum expected deviation 1%), if the
VCO input is held at a constant DC level. A LOW level at
the inhibit input (INH) enables the VCO and demodulator,
while a HIGH level turns both off to minimize standby
power consumption.
The only difference between the HC and HCT versions is
the input level specification of the INH input. This input
disables the VCO section. The sections of the comparator
are identical, so that there is no difference in the
SIG
IN
(pin 14) or COMP
IN
(pin 3) inputs between the HC
and HCT versions.
The signal input (SIG
IN
) can be directly coupled to the
self-biasing amplifier at pin 14, provided that the signal
swing is between the standard HC family input logic levels.
Capacitive coupling is required for signals with smaller
swings.
Phase comparator 1 (PC1)
This is an EXCLUSIVE-OR network. The signal and
comparator input frequencies (f
i
) must have a 50% duty
factor to obtain the maximum locking range. The transfer
characteristic of PC1, assuming ripple (f
r
= 2f
i
) is
V
CC
suppressed, is: V
DEMOUT
=
----------
( φ
SIGIN
–
φ
COMPIN
)
-
π
where V
DEMOUT
is the demodulator output at pin 10;
V
DEMOUT
= V
PC1OUT
(via low-pass filter).
V
CC
The phase comparator gain is: K
p
=
----------
(
V˙
⁄
r
)
.
-
π
The average output voltage from PC1, fed to the VCO
input via the low-pass filter and seen at the demodulator
output at pin 10 (V
DEMOUT
), is the resultant of the phase
differences of signals (SIG
IN
) and the comparator input
(COMP
IN
) as shown in Fig.6. The average of V
DEMOUT
is
equal to
1
⁄
2
V
CC
when there is no signal or noise at
SIG
IN
and with this input the VCO oscillates at the centre
frequency (f
o
). Typical waveforms for the PC1 loop locked
at f
o
are shown in Fig.7.
Philips Semiconductors
Product specification
Phase-locked-loop with VCO
The frequency capture range (2f
c
) is defined as the
frequency range of input signals on which the PLL will lock
if it was initially out-of-lock. The frequency lock range
(2f
L
) is defined as the frequency range of input signals on
which the loop will stay locked if it was initially in lock. The
capture range is smaller or equal to the lock range.
With PC1, the capture range depends on the low-pass
filter characteristics and can be made as large as the lock
range.
This configuration retains lock even with very noisy input
signals. Typical behaviour of this type of phase
comparator is that it can lock to input frequencies close to
the harmonics of the VCO centre frequency.
74HC/HCT4046A
and comparator inputs are equal in both phase and
frequency. At this stable point the voltage on C2 remains
constant as the PC2 output is in 3-state and the VCO input
at pin 9 is a high impedance. Also in this condition, the
signal at the phase comparator pulse output (PCP
OUT
) is a
HIGH level and so can be used for indicating a locked
condition.
Thus, for PC2, no phase difference exists between
SIG
IN
and COMP
IN
over the full frequency range of the
VCO. Moreover, the power dissipation due to the low-pass
filter is reduced because both p and n-type drivers are
“OFF” for most of the signal input cycle. It should be noted
that the PLL lock range for this type of phase comparator
is equal to the capture range and is independent of the
low-pass filter. With no signal present at SIG
IN
the
VCO adjusts, via PC2, to its lowest frequency.
Phase comparator 2 (PC2)
This is a positive edge-triggered phase and frequency
detector. When the PLL is using this comparator, the loop
is controlled by positive signal transitions and the duty
factors of SIG
IN
and COMP
IN
are not important. PC2
comprises two D-type flip-flops, control-gating and a
3-state output stage. The circuit functions as an up-down
counter (Fig.5) where SIG
IN
causes an up-count and
COMP
IN
a down-count. The transfer function of PC2,
assuming ripple (f
r
= f
i
) is suppressed,
V
CC
is: V
DEMOUT
=
----------
( φ
SIGIN
–
φ
COMPIN
)
-
4π
where V
DEMOUT
is the demodulator output at pin 10;
V
DEMOUT
= V
PC2OUT
(via low-pass filter).
V
CC
The phase comparator gain is: K
p
=
----------
(
V
⁄
r
)
.
-
4π
V
DEMOUT
is the resultant of the initial phase differences of
SIG
IN
and COMP
IN
as shown in Fig.8. Typical waveforms
for the PC2 loop locked at f
o
are shown in Fig.9.
When the frequencies of SIG
IN
and COMP
IN
are equal but
the phase of SIG
IN
leads that of COMP
IN
, the p-type
output driver at PC2
OUT
is held “ON” for a time
corresponding to the phase difference (φ
DEMOUT
). When
the phase of SIG
IN
lags that of COMP
IN
, the n-type driver
is held “ON”.
When the frequency of SIG
IN
is higher than that of
COMP
IN
, the p-type output driver is held “ON” for most of
the input signal cycle time, and for the remainder of the
cycle both n and p- type drivers are ”OFF” (3-state). If the
SIG
IN
frequency is lower than the COMP
IN
frequency, then
it is the n-type driver that is held “ON” for most of the cycle.
Subsequently, the voltage at the capacitor (C2) of the
low-pass filter connected to PC2
OUT
varies until the signal
Phase comparator 3 (PC3)
This is a positive edge-triggered sequential phase detector
using an RS-type flip-flop. When the PLL is using this
comparator, the loop is controlled by positive signal
transitions and the duty factors of SIG
IN
and COMP
IN
are
not important. The transfer characteristic of PC3,
assuming ripple (f
r
= f
i
) is suppressed,
V
CC
is: V
DEMOUT
=
----------
( φ
SIGIN
–
φ
COMPIN
)
-
2π
where V
DEMOUT
is the demodulator output at pin 10;
V
DEMOUT
= V
PC3OUT
(via low-pass filter).
V
CC
The phase comparator gain is: K
p
=
----------
(
V
⁄
r
)
.
-
2π
The average output from PC3, fed to the VCO via the
low-pass filter and seen at the demodulator output at
pin 10 (V
DEMOUT
), is the resultant of the phase differences
of SIG
IN
and COMP
IN
as shown in Fig.10. Typical
waveforms for the PC3 loop locked at f
o
are shown in
Fig.11.
The phase-to-output response characteristic of PC3
(Fig.10) differs from that of PC2 in that the phase angle
between SIG
IN
and COMP
IN
varies between 0° and
360° and is 180° at the centre frequency. Also PC3 gives
a greater voltage swing than PC2 for input phase
differences but as a consequence the ripple content of the
VCO input signal is higher. The PLL lock range for this type
of phase comparator and the capture range are dependent
on the low-pass filter. With no signal present at SIG
IN
the
VCO adjusts, via PC3, to its lowest frequency.
1997 Nov 25
3
Philips Semiconductors
Product specification
Phase-locked-loop with VCO
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C
74HC/HCT4046A
TYPICAL
SYMBOL
f
o
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz.
f
o
= output frequency in MHz.
C
L
= output load capacitance in pF.
V
CC
= supply voltage in V.
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs.
2. Applies to the phase comparator section only (VCO disabled). For power dissipation of the VCO and demodulator
sections see Figs 22, 23 and 24.
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
APPLICATIONS
•
FM modulation and demodulation
•
Frequency synthesis and multiplication
•
Frequency discrimination
•
Tone decoding
•
Data synchronization and conditioning
•
Voltage-to-frequency conversion
•
Motor-speed control.
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”.
PARAMETER
VCO centre frequency
input capacitance (pin 5)
power dissipation capacitance per
package
notes 1 and 2
CONDITIONS
HC
C1 = 40 pF; R1 = 3 kΩ; V
CC
= 5 V 19
3.5
24
HCT
19
3.5
24
MHz
pF
pF
UNIT
1997 Nov 25
4
Philips Semiconductors
Product specification
Phase-locked-loop with VCO
PIN DESCRIPTION
PIN NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SYMBOL
PCP
OUT
PC1
OUT
COMP
IN
VCO
OUT
INH
C1
A
C1
B
GND
VCO
IN
DEM
OUT
R
1
R
2
PC2
OUT
SIG
IN
PC3
OUT
V
CC
NAME AND FUNCTION
phase comparator pulse output
phase comparator 1 output
comparator input
VCO output
inhibit input
capacitor C1 connection A
capacitor C1 connection B
ground (0 V)
VCO input
demodulator output
resistor R1 connection
resistor R2 connection
phase comparator 2 output
signal input
phase comparator 3 output
positive supply voltage
74HC/HCT4046A
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
1997 Nov 25
5
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