CAT1232LP/CAT1832
5V and 3.3V Supply Monitor, Watchdog Timer,
Manual Reset, with Active High & Low Resets
FEATURES
I
Selectable reset voltage tolerance
DESCRIPTION
The CAT1232LP and CAT1832 microprocessor
supervisors can halt and restart a “hung-up” or “stalled”
microprocessor, restart a microprocessor after a power
failure, and debounce a manual/push-button micro-
processor reset switch. The devices are drop in
replacements for the Maxim/Dallas Semiconductor
DS1232LP and DS1832 supervisors
Precision reference and comparator circuits monitor the
5V or 3.3V system power supply voltage, V
CC
. During
power-up or when the power supply falls outside
selectable tolerance limits, both the RESET and
RESET
become active. After the power supply voltage rises
above the RESET threshold voltage, the reset signals
remain active for a minimum of 250ms, allowing the
power supply and system processor to stabilize. The
trip-point tolerance input, TOL, selects the trip level
tolerance to be either 5% or 10% for the CAT1232LP 5V
supply and 10% or 20% for the CAT1832 3.3V supply.
Each device has a push-pull, active HIGH reset output.
The CAT1232LP also has an open drain, active LOW
reset output while the CAT1832 also has a push-pull,
active LOW reset output.
A debounced manual reset input activates the reset
outputs and holds them active for a minimum period of
250ms after being released.
Also included is a watchdog timer to reset a
microprocessor that has stopped due to a software or
hardware failure. Three watchdog time-out periods are
selectable: 150ms, 600ms and 1.2sec. If the
ST
input is
not strobed low before the watchdog time out period
expires, the reset signals become active for a minimum
of 250ms.
— CAT1232LP for 5V supply
— CAT1832 for 3.3V supply
I
Selectable watchdog period:
150ms, 600ms or 1.2 sec
I
Two reset outputs
— Active high, push-pull reset output
— Active low, open-drain reset output
(CAT1232LP)
— Active low, push-pull reset output (CAT1832)
I
Debounced manual push-button reset
I
Compact SOIC and MSOP packages
APPLICATIONS
I
Microprocessor Systems
I
Portable Equipment
I
Controllers
I
Single Board Computers
I
Instrumentations
I
Telecommunications
FUNCTIONAL DIAGRAM
VCC
TOL
V
CC
Reference
40kΩ
RESET
PBRST
TD
ST
Push Button Debounce
Watchdog Timebase Selection
Watchdog Transition Detector
Reset &
Watchdog Timer
RESET
(CAT1832)
Tolerance Selection
(CAT1232LP)
RESET
+
–
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25089, Rev. B
CAT1232LP/CAT1832
ORDERING INFORMATION
Solder Plate Lead
Finish
Ordering Part
Number
CAT1232LPP
CAT1232LPJ
CAT1232LPS
CAT1232LPR
CAT1232LPJ-T13
CAT1232LPS-T13
CAT1232LPR-T13
CAT1832P
CAT1832S
CAT1832R
CAT1832S-T13
CAT1832R-T13
Green Sn Lead
Finish
Ordering Part
Number
CAT1232LPL
CAT1232LPW
CAT1232LPV
CAT1232LPZ
CAT1232LPW-T13
CAT1232LPV-T13
CAT1232LPZ-T13
CAT1832L
CAT1832V
CAT1832Z
CAT1832V-T13
CAT1832Z-T13
Green NiPdAu Lead
Finish
Ordering Part
Number
CAT1232LPL-G
CAT1232LPW-G
CAT1232LPV-G
CAT1232LPZ-G
CAT1232LPW-GT2
CAT1232LPV-GT2
CAT1232LPGZ-GT25
CAT1832L-G
CAT1832W-G
CAT1832Z-G
CAT1832W-GT2
CAT1832Z-GT25
Package
8-lead, DIP
16-lead, SOIC
8-lead, SOIC
MSOP
16-lead, SOIC
8-lead, SOIC
MSOP
8-lead, DIP
8-lead, SOIC
MSOP
8-lead, SOIC
MSOP
Parts per
Tube
50
47
100
100
—
—
—
50
100
100
—
—
Parts Per
Reel
—
—
—
—
2,000
2,000
2,500
—
—
—
2,000
2,500
Reel Size
(inch)
—
—
—
—
13
13
13
—
—
—
13
13
The “-G” NiPdAu Lead Finish is only available on the Green packager versions of this device.
PIN CONFIGURATION
8-Lead SOIC/MSOP/DIP
PBRST 1
TD 2
TOL 3
GND 4
8 VCC
7 ST
6 RESET
5 RESET
16-Lead SOIC
NC
PBRST
NC
TD
NC
TOL
NC
GND
1
2
3
4
5
6
7
8
16 NC
15 VCC
14 NC
13 ST
12 NC
11 RESET
10 NC
9 RESET
PIN DESCRIPTION
Pin Number
Pin Number
8-Lead Package 16-Lead Package
1
2
2
4
Name
PBRST
TD
Function
Debounced manual pushbutton reset input
Watchdog typical time delay selection:
a) t
TD
= 150ms for TD = GND
b) t
TD
= 600ms for TD = Open
c) t
TD
= 1200ms for TD = V
CC
CAT1232LP TOL selects 5% (TOL = GND) or 10% (TOL = V
CC
) trip
point tolerance. CAT1832 TOL selects 10% (TOL = GND) or 20% TOL =
V
CC
) trip point tolerance.
Ground
Active HIGH reset output. RESET is active
1. If V
CC
falls below the reset voltage trip point
2. If
PBRST
is low
3. If
ST
is not strobed low before the timeout period set by TD expires.
4. During power-up.
Active LOW reset output. (See RESET)
Strobe Input
Power Supply
No internal connection
3
6
TOL
4
5
8
9
GND
RESET
6
7
8
11
13
15
1, 3. 5, 7, 10, 12,
14, 16
RESET
ST
V
CC
NC
Doc. No. 25089, Rev. B
2
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT1232LP/CAT1832
ABSOLUTE MAXIMUM RATINGS*
Voltage on V
CC
....................................... -0.5V to 7.0V
Voltage on
ST
and TD ................. -0.5V to V
CC
+ 0.5V
Voltage on
PBRST, RESET
and RESET ............................ -0.5V to V
CC
+ 0.5V
ELECTRICAL CHARACTERISTICS
Unless otherwise stated, 1.0V
≤
V
CC
≤
5.5V and over the operating temperature range of -40°C to +85°C. All
voltages are referenced to ground.
Symbol Parameter
V
CC
I
CC1
V
IH
V
IL
V
CCTP
V
CCTP
V
CCTP
V
CCTP
t
TD
t
TD
t
TD
V
OH
I
OH
I
OL
I
IL
R
PU
C
IN
C
OUT
t
PB
t
RST
t
ST
t
RPD
t
F
t
PDLY
Supply Voltage
Supply Current
V
CC
= 5.5V, CAT1232LP
V
CC
= 3.6V, CAT1832
(5)
Maximum Junction Temperature ...................... 125°C
Storage Temperature Range ............ -65°C to +150°C
Lead Soldering Temperature (10 sec) .............. 300°C
Operating Temperature Range ........... -40°C to +85°C
Conditions
Min
1.0
Typ
35
20
Max
5.5
50
35
V
CC
+ 0.3V
0.8
Units
V
µA
V
V
ST
and
PBRST
Input High Level
ST
and
PBRST
Input Low Level
V
CC
Trip Point (TOL = GND)
V
CC
Trip Point (TOL = V
CC
)
V
CC
Trip Point (TOL = GND)
V
CC
Trip Point (TOL = V
CC
)
Watchdog Time-Out Period
Watchdog Time-Out Period
Watchdog Time-Out Period
Output Voltage
Output Current
Output Current
Input Leakage
Internal Pull-Up Resistor
Input Capacitance
Output Capacitance
2
V
CC
- 0.4V
– 0.3
(6)
V
CC
= 5.5V, CAT1232LP
V
CC
= 3.6V, CAT1832
CAT1232LP
CAT1232LP
CAT1832
CAT1832
TD = GND
TD = V
CC
TD floating
I = – 500µA
(3)
Output = 2.4V
(2)
Output = 0.4V,
(1)
(1)
0.5
4.50
4.25
2.80
2.47
62.5
500
250
V
CC
- 0.5V
4.62
4.37
2.88
2.55
150
1200
600
V
CC
- 0.1V
– 350
10
– 1.0
32
40
1.0
55
5
7
4.74
4.49
2.97
2.64
250
2000
1000
V
V
V
V
ms
ms
ms
V
µA
mA
µA
kΩ
pF
pF
ms
600
5
20
1000
8
ms
ns
µs
µs
ms
ms
ns
PBRST
Manual Reset
Minimum Low Time
Reset Active Time
PBRST
= V
IL
20
250
t
RPU
t
R
ST
Pulse Width
V
CC
Fail Detect to
RESET or
RESET
V
CC
Slew Rate
PBRST
Stable LOW to
RESET and
RESET
Active
V
CC
Detect to RESET or
RESET
Inactive
V
CC
Slew Rate
(4)
20
20
t
RISE
= 5µs
4.25V to 4.75V
250
0
600
1000
Notes:
(1)
PBRST
is internally pulled HIGH to V
CC
through a nominal 40kΩ
resistor (R
PU
).
(2)
RESET
is an open drain output on the CAT1232LP.
(3) RESET remains within 0.5V of V
CC
on power-down until V
CC
falls
below 2V. RESET remains within 0.5V of ground on power-down
until V
CC
falls below 2.0V.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
(4) Must not exceed the minimum watchdog time-out period (t
TD
).
The watchdog circuit cannot be disabled. To avoid a reset,
ST
must be strobed.
(5) Measured with V
CC
≥
2.7V.
(6) Measured with V
CC
< 2.7V.
Doc. No. 25089, Rev. B
3
CAT1232LP/CAT1832
TYPICAL CHARACTERISTICS
For the CAT1232LP, V
CC
= 5V and T
AMB
= 25°C unless otherwise stated.
Threshold Voltage vs. Temperature (10% TOL)
THRESHOLD VOLTAGE (V)
Threshold Voltage vs. Temperature (5% TOL)
THRESHOLD VOLTAGE (V)
4.630
4.625
TOL = GND (5%)
4.620
4.615
4.610
-50
4.450
4.445
TOL = Vcc (10%)
4.440
4.435
4.430
-50
0
50
100
TEMPERATURE (°C)
0
50
100
TEMPERATURE (°C)
Supply Current vs. Temperature
40
30
20
10
0
-50
Vcc = 5.5V
Vcc = 4.5V
Reset Active Time vs. Temperature
800
RESET ACTIVE TIME (ms)
SUPPLY CURRENT (µA)
700
600
500
400
300
-50
Vcc = 5.5V
TD = open
Vcc = 4.5V
0
50
100
0
50
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Reset Active Time Waveform
Transient Response
Doc. No. 25089, Rev. B
4
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT1232LP/CAT1832
APPLICATION INFORMATION
SUPPLY VOLTAGE MONITOR
Reset Signal Polarity and Output Stage Structure
RESET
is an active LOW signal. It is developed with an
open drain driver in the CAT1232LP. A pull-up resistor
is required, typical values are 10kΩ to 50kΩ. The
CAT1832 uses a CMOS push-pull output stage for the
RESET.
RESET is an active High signal developed by a CMOS
push-pull output stage and is the logical opposite to
RESET.
Trip Point Tolerance Selection
The TOL input is used to select the V
CC
trip point
threshold. This selection is made connecting the TOL
input to ground or V
CC
. Connecting TOL to Ground
makes the V
CC
trip threshold 4.62V for the CAT1232LP
and 2.88V for the CAT1832.
Connecting TOL to VCC makes the VCC trip threshold
4.37V for the CAT1232LP and 2.55V for the CAT1832.
After V
CC
has risen above the trip point set by TOL,
RESET and
RESET
remain active for a minimum time
period of 250ms.
On power-down, once V
CC
falls below the reset threshold
the RESET outputs will remain active and are guaranteed
valid down to a V
CC
level of 1.0V.
Tolerance
Select
Voltage
CAT1232LP
TOL = V
CC
CAT1232LP
TOL = GND
CAT1832
TOL = V
CC
CAT1832
TOL = GND
Trip Point
Tolerance
10 %
5%
20 %
10 %
Trip Point Voltage (V)
MIN
4.25
4.50
2.47
2.80
NOMINAL
4.37
4.62
2.55
2.88
MAX
4.49
4.74
2.64
2.97
t
R
V
CCTP(MAX)
V
CCTP
t
F
V
CC
V
CCTP(MAX)
V
CCTP
V
CCTP(MIN)
V
CCTP(MIN)
V
CC
t
RPU
RESET
V
OH
RESET
t
RPD
V
OL
RESET
RESET
V
OH
V
OL
Figure 1. Timing Diagram: Power Up
Figure 2. Timing Diagram: Power Down
Manual Reset Operation
Push-button input,
PBRST,
allows the user to issue
reset signals. The pushbutton input is debounced and is
pulled high through an internal 40kΩ resistor.
When
PBRST
is held low for the minimum time of 20 ms,
both resets become active and remain active for a
minimum time period of 250ms after
PBRST
returns
high.
No external pull-up resistor is required, since
PBRST
is
pulled high by an internal 40kΩ resistor.
PBRST
can be driven from a TTL or CMOS logic line or
short-ed to ground with a mechanical switch.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. 25089, Rev. B
FPGA/CPLD
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