SB-36410IX
Make sure the next
Card you purchase
has...
®
EIGHT CHANNEL RESOLVER /
SYNCHRO-TO-DIGITAL PMC CARD
FEATURES
•
1.3 Arc Minute Accuracy
•
Synthesized Reference
•
Programmable for 2V Direct, or
11.8V/90V Synchro or Resolver inputs
•
Independent Reference Inputs for
each Channel
•
Programmable Resolution: 10, 12, 14
and 16 Bits
•
Programmable Bandwidth of 15/45Hz
or 100/300Hz
•
Built-In-Test and Velocity Outputs
•
-40° to +85°C Temperature Range
DESCRIPTION
The SB-36410IX provides either 4 or 8 channels of fully independent
Resolver- or Synchro-to-Digital conversion on a PMC card that paral-
lel mounts on a host VME or cPCI carrier card. The heart of this card
is DDC's proven RD-19230FX monolithic converter.
The card offers programmable selection of High or Low Bandwidth
range. Resolution can be programmed for 10, 12, 14, or 16-bit, with
1.3 Arc minute accuracy. A wide reference input voltage range is sup-
ported (see the specification page). The internal synthesized refer-
ence corrects for rotor-to-stator phase shift errors of up to 45°.
Incremental encoder emulation signals have independent resolution
control.
•
Internal Incremental Optical Encoder
Emulation with Independent
Resolution Control
•
Universal (3.3V or 5V) PCI Signalling
•
DLL's and Libraries for Windows
®
2000/XP and Windows NT
®
- Contact
Factory for availability of Linux
®
APPLICATIONS
The SB-36410IX PMC card is an ideal COTS solution for use in VME
or cPCI control systems employing a 33 MHz bus. The card also pro-
vides an ideal solution for encoder-based systems that have Synchro/
Resolver inputs. Typical applications include motor control, machine
tool control, antenna control, robotics, and process control.
FOR MORE INFORMATION CONTACT:
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
Technical Support:
1-800-DDC-5757 ext. 7771
All trademarks are the property of their respective owners.
© 2002 Data Device Corporation
THIN-FILM
RESISTOR
NETWORK
PMC Card
VME / cPCI
Card
Data Device Corporation
www.ddc-web.com
Self Test Generator
Channel 1
SIN
COS
RH
RL
INPUT
SCALING
RESOLVER-TO-
DIGITAL
CONVERTER
SIN
COS
RH
RL
S1
S2
S3
S4
RH
RL
BIT
RD-19230
MONOLITHIC
POSITION AND BIT DATA
P4
RD-19230
MONOLITHIC
RESOLVER-TO-
DIGITAL
CONVERTER
POSITION
AND BIT
DATA
P1 / P2
Channel 8
INPUT
SCALING
INTERNAL
REGISTER
DATA
2
S1
S2
S3
S4
RH
RL
BIT
Channel 8
ADDRESS
DECODER
ADDRESS
A
B
ZI
VEL
BIT
P5
Channel 1
A
B
ZI
VEL
BIT
SB-36410IX
J-4/10-0
PCI BUS
FIGURE 1. SB-36410IX BLOCK DIAGRAM
TABLE 1. SB-36410IX SPECIFICATIONS
These specifications apply over the rated power supply, temperature, and reference
frequency ranges; 10% signal amplitude variation and 10% harmonic distortion.
PARAMETER
RESOLUTION
ACCURACY
-XX2
SIGNAL INPUT
Option #
Synchro
Zin Line to Line
Zin each Line to Ground
Resolver
Zin Single Ended
Zin Differential
Common Mode Range
REFERENCE INPUT (RH, RL)
Signal Input Option #
Carrier Frequency
Type
Voltage Range
Input Impedance
• differential
• single ended
Common-mode Range
DIGITAL OUTPUTS
A, B, Zero Index (ZI)
Drive Capability
After set into A quad B mode
PCI INTERFACE
Max Bit Size
Max Clock Speed
Bus Signaling
Vdc
A typical
Vrms
L-L
Ohms
Ohms
Vrms
L-L
Ohms
Ohms
V
Option 0
—
—
—
2 Vrms direct (note 3)
10M min || 20pf (note 1)
N/A
N/A
Option 0
360 - 7k
Differential
2 - 40
100k
50k
50
Minutes
UNIT
Bits
47-1k (note 2)
1 + 1 LSB
VALUE
10, 12, 14 or 16 programmable (note 4)
1k-4k
1 + 1 LSB
Solid State
Option 1, 2
11.8
52k
35k
11.8
70k
140k
30 max
Solid State
Hz
Vrms
Ohms
Ohms
Vpeak
Option 1, 2
360 - 7k
Differential
2 - 40
100k
50k
50
Option 3
360 - 1k
Differential
50 - 130
300k
200k
200
Option 4
47 - 400
Differential
50 - 130
300k
200k
200
Option 3, 4
90
195k
130k
—
—
—
—
4k-7k
2 + 1 LSB
50pf+
Logic 0: 1 TTL load, 1.6mA at 0.4V max
Logic 1: 10 TTL loads, = 0.4mA at 2.8V min
Logic 0: 100mV max driving CMOS
Logic 1: +5V supply minus 100mV min driving CMOS
32
33 MHz
3.3V/5V universal bus voltage
3.3V Supply
0.06
Air Cooled
5.0V Supply
0.30
POWER SUPPLY (NOTE 5)
Voltage
Current
COOLING METHOD
TEMPERATURE RANGE
Operating
-30X
-20X
Storage
-30X
-20X
PHYSICAL
CHARACTERISTICS
Size
Weight
Note
Note
Note
Note
Note
1:
2:
3:
4:
5:
°C
°C
°C
°C
0 to +70
-40 to +85
-20 to +100
-50 to +150
in.
(mm.)
oz
(g)
6.00 x 2.91 x 0.54
152.5 x 74 x 13.8
3.88 (max)
110 (max)
|| = “in parallel with”
If the frequency is between 47 and 1 kHz, then there will be 1 LSB of jitter.
Direct input requires SIN input, COS input, and a common ground.
Signal input option #4 (90V Synchro 60Hz) not recommended for use in 16 bit resolution mode due to excessive jitter.
5 Volt supplies are required for R/D converter operation during 3.3V signalling mode.
Data Device Corporation
www.ddc-web.com
3
SB-36410IX
J-4/10-0
INTRODUCTION
The SB-36410IX PMC card contains either 4 or 8 channels of
Synchro/Resolver-to-Digital converters with independent refer-
ence signals. PMC cards are intended to be used as a daughter
board to be parallel mounted on a host VME or cPCI board. The
PMC card uses the "VME or cPCI" PCI bus for data transfer.
The heart of each channel is DDC's RD-19230FX converter,
which has a long history of proven performance. For complete
converter specifications, the RD-19230 data sheet can be down-
loaded from the DDC web site.
Transformer (CT) compares the analog input signals (
θ
) with the
digital output (
φ
), resulting in an error signal proportional to the
sine of the angular difference. The CT uses a combination of
amplifiers, switches, logic and capacitors in precision ratios to
perform the calculation.
The converter accuracy is limited by the precision of the comput-
ing elements in the CT. Instead of a traditional precision resistor
network, this converter uses capacitors with precisely controlled
ratios. Sampling techniques are used to eliminate errors due to
voltage drift and op-amp offsets.
The error processing is performed using the industry standard
technique for Type II tracking converters. The DC error is inte-
grated yielding a velocity voltage which in turn drives a voltage
controlled oscillator (VCO). This VCO is an incremental integra-
tor (constant voltage input to position rate output) which, togeth-
er with the velocity integrator, forms a Type II servo feedback
loop. A lead in the frequency response is introduced to stabilize
the loop and another lag at higher frequency is introduced to
reduce the gain and ripple at the carrier frequency and above.
The settings of the various error processor gains and break fre-
quencies are done with external resistors and capacitors so that
the converter loop dynamics can be easily controlled by the
user.
THEORY OF OPERATION
Each channel utilizes a mixed signal CMOS IC containing analog
input and digital output sections. Precision analog circuitry is
merged with digital logic to form a complete high-performance
tracking resolver-to-digital converter. For user flexibility and con-
venience, the converter bandwidth, dynamics, and velocity scal-
ing are externally set with passive components.
FIGURE 1 shows the Functional Block Diagram for the
SB-36410IX card. The analog conversion electronics require
±5VDC power supplies. The -5VDC is supplied by the on-chip
charge pump. This means that only +5VDC and +3.3VDC are
required for the SB-36410IX card. The converter front-end con-
sists of differential sine and cosine input amplifiers which are
protected up to ±25V with 2k resistors and diode clamps to the
±5VDC supplies. By performing the following trigonometric iden-
tity, SIN
θ(
COS
φ)
- COS
θ
(SIN
φ
) = SIN(
θ
-
φ
), the Control
TRANSFER FUNCTION AND BODE PLOT
The dynamic performance of the converter can be determined
from its Transfer Function Block Diagrams and Bode Plots (open
and closed loop). These are shown in FIGURES 2, 3, and 4.
TABLE 2. DYNAMIC CHARACTERISTICS
TYPE
Resolution (bits)
Bandwidth (Hz)
Low
High
32
.125
Low BW
BW
A1
A2
A
B
Notes:
15
0.15
8.2k
35
18
10
*
45
8
.5
60 HZ NOMINAL
12
*
**
2
2
High BW
45
1.25
8.2k
101
50
14
15
**
.5
8
320
.0125
Low BW
100
0.85
81k
260
132
16
10
*
300
80
.05
400 HZ NOMINAL
12
*
**
20
.2
High BW
300
5.80
81k
690
345
14
100
**
5
.8
16
Tracking Rate (rps)
Scale Factor (Volts/rps)
TYPE
60 HZ NOMINAL
400 HZ NOMINAL
* Not recommended - Low bandwidths in low resolutions may induce spin around and the part will not settle
** High bandwidths in high resolutions may be used with carrier frequencies above 1.5kHz
Data Device Corporation
www.ddc-web.com
4
SB-36410IX
J-4/10-0
RB C
BW
VEL
R
V
Values for the transfer function block can be obtained from TABLE
2.
C
BW
/10
VEL SJ1
VEL
-VCO
50 pf
C
VCO
CT
RESOLVER
INPUT
(θ)
+
R1
GAIN
DEMOD
1
±1.25 V
THRESHOLD
VCO
-
16 BIT
UP/DOWN
COUNTER
A
2
S +1
B
Open Loop Transfer Function =
S
2
S +1
10B
The open loop transfer function is as follows:
(
(
)
)
C
S
F
S
11 mV/LSB
H=1
DIGITAL
OUTPUT
(
φ)
where A is the gain coefficient and A
2
= A
1
x A
2
FIGURE 2. TRANSFER FUNCTION BLOCK DIAGRAM #1
and B is the frequency of lead compensation.
- Error Gradient = 0.011 volts per LSB (CT + Error Amp + Demod)
- Integrator Gain = Cs Fs volts per second per volt
1.1 C
BW
- VCO Gain =
1
LSBs per second per volt
1.25 R
V
C
VCO
ERROR PROCESSOR
RESOLVER
INPUT
(θ)
+
-
CT
e
A1 S + 1
B
S
S +1
10B
VELOCITY
OUT
VCO
A
2
S
DIGITAL
POSITION
OUT (φ)
H=1
where: Cs = 10 pF
Fs = 67 kHz
C
VCO
= 50 pF
FIGURE 3. TRANSFER FUNCTION BLOCK DIAGRAM #2
The components of gain coefficient are error gradient, integrator
gain, and VCO gain. These can be broken down as follows:
SYNTHESIZED REFERENCE
The synthesized reference eliminates errors due to phase shift
between the reference and the signal inputs up to 45°. Quadrature
voltages in a resolver or synchro are by definition the resulting
90° fundamental signal in the nulled out error voltage (e) in the
converter. Due to the inductive nature of resolvers and synchros,
their output signals lead the reference input signal (RH and RL).
When an uncompensated reference signal is used to demodu-
late the control transformer’s output, Quadrature voltages are not
completely eliminated. Therefore this is the perfect solution to
combat phase shift error to 45°.
2d
-1
GAIN = 4
2A
OPEN LOOP
B
A
-6
db
c
b/o
(CRITICALLY DAMPED)
(B = A/2)
t
/oc
t
ω
(rad/sec)
10B
GAIN = 0.4
TRANSIENT PROTECTION
f
BW
= BW (Hz) =
2A
2 2A
2A
π
CLOSED LOOP
ω
(rad/sec)
FIGURE 4. BODE PLOTS
Systems using the 90 V line-to-line inputs may have voltage
transients which exceed the maximum specification for the thin-
film resistor network (500 V). The 90 V may be derived from
poorly regulated 115 V Power Supplies, which have various high
current loads. These loads switch on and off, thus causing spikes
and transients in regulation. These transients can destroy the
input thin-film resistor network. Therefore, 90 V line-to-line solid-
state input (DDC-49590) thin-film may be protected by installing
voltage suppressors as shown in Figure 5 and Figure 6. Voltage
transients are also likely to occur whenever the synchro or
resolver input is switched on and off. For instance, a 1000 V
transient can be generated when the primary of a control trans-
mitter (CX) or torque transmitter (TX) driving a synchro or
resolver input is opened.
SB-36410IX
J-4/10-0
Data Device Corporation
www.ddc-web.com
5
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