HY23V04200
Description
256K X 16/ 512K X 8 BIT
CMOS MASK ROM
The HY23V04200 high performance read only memory is organized either as 524,288 x 8 bit
(byte mode) or as 262,144 x 16 bit(word mode) followed by BHE mode select. The low power
feature allows the battery operation. The large size of 4M bit memory density is ideal for
character generator, data or program memory in micro-processor application. And a high speed
access of 70/100/120ns(max) is most suitable to the system using a high speed micro-computer
by 16bits. The HY23V04200 is packaged 40pin DIP or 40 pin SOP.
Key features
• Switchable Organization
Byte Mode : 524,288 X 8 bit
Word Mode : 262,144 X 16 bit
• Single 3.3V power supply operation
• Access Time : 70/100/120ns (Max)
• Standby Current : 50 (Max)
• Operating Current : 35 (Max)
• TTL compatible inputs and outputs
• 3-State outputs for wired-OR expansion
• Word or Byte switchable by BHE pin
• Programmable CE or OE pin
• Fully static operation
• Package
HY23V04200D
: 40pin Plastic DIP(600 mil)
HY23V04200S
: 40pin Plastic SOP(500mil)
¡
Pin Description
Pin
A0~A17
Q0~Q14
Q15/A-1
BHE
CEB*
OEB*
VCC
VSS
Function
Address inputs
Data Outputs
Output Q15(Word Mode)/
LSB Address(Byte Mode)
Byte High Enable input
(Word/Byte selection)
Chip Enable input
Output Enable input
Power supply
Ground
Pin Configuration
A17
A7
A6
A5
A4
A3
A2
A1
A0
CEB
VSS
OEB
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A17
A7
A6
A5
A4
A3
A2
A1
A0
CEB
VSS
OEB
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
* User selectable polarity
40
39
38
37
36
35
34
33
32
40DIP
31
30
29
28
27
26
25
24
23
22
21
A8
A9
A10
A11
A12
A13
A14
A15
A16
BHE
VSS
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
1
2
3
4
5
6
7
8
40
39
38
37
36
35
34
33
A8
A9
A10
A11
A12
A13
A14
A15
A16
BHE
VSS
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
9
32
10
40SOP
31
11
30
12
29
13
28
14
27
15
16
17
18
19
20
26
25
24
23
22
21
HY23V04200D
HY23V04200S
Rev0 Page 1 of 6
ARTCHIPs
HY23V04200
Absolute Maximum Ratings
Symbol
T
A
T
STG
V
CC
V
OUT
V
IN
Parameter
Ambient Operating Temperature
Storage Temperature
Supply Voltage to Ground Potential
Output Voltage
Input Voltage
Rating
-10 ~ 80
-55 ~ 150
-0.3 ~ 4.5
-0.3~Vcc+0.3
-0.3~Vcc+0.3
256K X 16/ 512K X 8 BIT
CMOS MASK ROM
Unit
O
C
C
O
V
V
V
Stress above those listed under “absolute maximum ratings” may cause permanent damage to the
device. These are stress ratings only. Functional operation of this device at these or any other
conditions above those indicated in the operational sections of this specification is not implied and
exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions(VCC=3.3
·
0.3V, T
A
=0~70
O
C )
Symbol
Vcc
Vss
V
IH
V
IL
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Min
3.0
0
2.2
-0.3
Typ
3.3
0
Max
3.6
0
Vcc+0.3
0.8
Unit
V
V
V
V
DC Electrical Characteristics(VCC=3.3
·
0.3V, T
A
=0~70
O
C )
Symbol
V
OH
V
OL
I
IL
I
OL
I
CC
Parameter
Output High Voltage
Output Low Voltage
Input Leakage Current
Output Leakage Current
Operating Supply Current
(tRC=100ns)
I
SB1
I
SB2
Standby Current(TTL)
Standby Current(CMOS)
Condition
I
OH
=-0.4mA
I
OL
=2.1mA
Min
2.4
Typ
Max
Unit
V
0.4
10
¡
V
uA
uA
mA
uA
uA
V
IN
=0V to V
CC
¡
V
OUT
=0V to V
CC
CEB=OEB=V
IL
All Output Open
CEB=V
IH
, all Output Open
CEB=V
CC
, all Output Open
10
35
500
50
Rev0 Page 3 of 6
ARTCHIPs
HY23V04200
Capacitance(T
A
=25
O
C , f=1.0MHz)
Symbol
C
I
C
O
Parameter
Input Capacitance
Output Capacitance
Condition
VIN = 0V
VOUT = 0V
Min
256K X 16/ 512K X 8 BIT
CMOS MASK ROM
Max
10
10
Unit
pF
pF
Capacitance is periodically sampled and not 100% tested
Function Table
MODE
Standby
16bit
Operating
L/H
8bit
Operating
L/H
L
Data output
(upper 8bit)
H/L
X
High-Z
CEB/CE
H/L
OEB/OE
X
BHE
X
H
Data output
(lower 8bit)
High-Z
H
Q0 ~ Q7
Q8 ~ Q14
High-Z
Data Out
L
Active
Q15 ~A-1
POWER
Standby
Output
Disable
X
AC Characteristics(VCC=3.3
·
0.3V, T
A
=0~70
O
C )
Symbol
tRC
tACE
tAA
tAOE
tOH
tHZ
tLZ
Parameter
Min
Read cycle time
Chip enable access time
Address access time
Output enable access time
Output hold time from address change
Output or chip disable to output High-Z
Output or chip Enable to output Low-Z
10
0
20
10
70
70
70
35
0
20
10
Max
Min
100
100
100
50
0
20
Max
Min
120
120
120
60
Max
ns
ns
ns
ns
ns
ns
ns
70ns
100ns
120ns
Unit
AC Test Condition
• Input pulse level
• Input rise and fall time
• Input and output timing level
• Output load
0.4V to 2.4V
10ns
1.5V
1 TTL gate and CL=100pF(70ns product CL=30pF)
Rev0 Page 4 of 6
ARTCHIPs
模拟电子
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