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TMS320VC5402
FIXED POINT DIGITAL SIGNAL PROCESSOR
SPRS079G − OCTOBER 1998 − REVISED OCTOBER 2008
D
Advanced Multibus Architecture With Three
D
D
Separate 16-Bit Data Memory Buses and
One Program Memory Bus
40-Bit Arithmetic Logic Unit (ALU),
Including a 40-Bit Barrel Shifter and Two
Independent 40-Bit Accumulators
17-
×
17-Bit Parallel Multiplier Coupled to a
40-Bit Dedicated Adder for Non-Pipelined
Single-Cycle Multiply/Accumulate (MAC)
Operation
Compare, Select, and Store Unit (CSSU) for
the Add/Compare Selection of the Viterbi
Operator
Exponent Encoder to Compute an
Exponent Value of a 40-Bit Accumulator
Value in a Single Cycle
Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
Data Bus With a Bus-Holder Feature
Extended Addressing Mode for 1M
×
16-Bit
Maximum Addressable External Program
Space
4K x 16-Bit On-Chip ROM
16K x 16-Bit Dual-Access On-Chip RAM
Single-Instruction-Repeat and
Block-Repeat Operations for Program Code
Block-Memory-Move Instructions for
Efficient Program and Data Management
Instructions With a 32-Bit Long Word
Operand
Instructions With Two- or Three-Operand
Reads
D
Arithmetic Instructions With Parallel Store
D
D
D
and Parallel Load
Conditional Store Instructions
Fast Return From Interrupt
On-Chip Peripherals
− Software-Programmable Wait-State
Generator and Programmable Bank
Switching
− On-Chip Phase-Locked Loop (PLL) Clock
Generator With Internal Oscillator or
External Clock Source
− Two Multichannel Buffered Serial Ports
(McBSPs)
− Enhanced 8-Bit Parallel Host-Port
Interface (HPI8)
− Two 16-Bit Timers
− Six-Channel Direct Memory Access
(DMA) Controller
Power Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions With
Power-Down Modes
CLKOUT Off Control to Disable CLKOUT
On-Chip Scan-Based Emulation Logic,
IEEE Std 1149.1
†
(JTAG) Boundary Scan
Logic
10-ns Single-Cycle Fixed-Point Instruction
Execution Time (100 MIPS) for 3.3-V Power
Supply (1.8-V Core)
Available in a 144-Pin Plastic Low-Profile
Quad Flatpack (LQFP) (PGE Suffix) and a
144-Pin Ball Grid Array (BGA) (GGU Suffix)
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
NOTE:This
data sheet is designed to be used in conjunction with the
TMS320C5000 DSP Family Functional Overview
(literature number SPRU307).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
† IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2008, Texas Instruments Incorporated
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77251−1443
1
TMS320VC5402
FIXED POINT DIGITAL SIGNAL PROCESSOR
SPRS079G − OCTOBER 1998 − REVISED OCTOBER 2008
TABLE OF CONTENTS
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Software-Programmable Wait-State Generator . . . . . . . . . 16
Programmable Bank-Switching Wait States . . . . . . . . . . . . 18
Parallel I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Enhanced 8-Bit Host-Port Interface . . . . . . . . . . . . . . . . . . . 19
Multichannel Buffered Serial Ports . . . . . . . . . . . . . . . . . . . . 20
Hardware Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 27
McBSP Control Registers And Subaddresses . . . . . . . . . . 29
DMA Subbank Addressed Registers . . . . . . . . . . . . . . . . . . 29
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Conditions . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parameter Measurement Information . . . . . . . . . . . . . . . . . .
Internal Oscillator With External Crystal . . . . . . . . . . . . . . . .
Divide-By-Two Clock Option (PLL Disabled) . . . . . . . . . . . .
Multiply-By-N Clock Option . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory and Parallel I/O Interface Timing . . . . . . . . . . . . . .
Ready Timing For Externally Generated Wait States . . . . .
HOLD and HOLDA Timings . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset, BIO, Interrupt, and MP/MC Timings . . . . . . . . . . . . .
Instruction Acquisition (IAQ), Interrupt Acknowledge
(IACK), External Flag (XF), and TOUT Timings . . . . .
Multichannel Buffered Serial Port Timing . . . . . . . . . . . . . . .
HPI8 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
35
35
36
37
37
38
39
40
46
50
51
53
55
62
66
REVISION HISTORY
REVISION
*
A
B
C
D
E
DATE
October 1998
April 1999
July 1999
September 1999
January 2000
August 2000
PRODUCT STATUS
Advanced Information
Advanced Information
Advanced Information
Advanced Information
Production Data
Production Data
Original
Revised to update characteristic data
Revised to update characteristic data
Revised to update characteristic data
Revised to release production data.
Added Table of Contents, Revision History, and corrected IDLE3
current on page 35.
Updated table of contents and revision history. Added notices con-
cerning JTAG (IEEE 1149.1) boundary scan test capability and re-
placed document support section on page 33. Added device and
development-support tool nomenclature section on page 34. Re-
placed Figure 9 on page 37. Replaced Figure 36 on page 65. Re-
placed mechanical section on page 66.
Terminal Functions table:
− Updated DESCRIPTION of TRST
− Added footnote about TRST
Mechanical Data section:
− Revised paragraph
− Mechanical drawings will be appended to this document via an
automated process
HIGHLIGHTS
F
February 2005
Production Data
G
October 2008
Production Data
2
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77251−1443
TMS320VC5402
FIXED POINT DIGITAL SIGNAL PROCESSOR
SPRS079G − OCTOBER 1998 − REVISED OCTOBER 2008
description
The TMS320VC5402 fixed-point, digital signal processor (DSP) (hereafter referred to as the 5402 unless
otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus
and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of
parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis
of the operational flexibility and speed of this DSP is a highly specialized instruction set.
Separate program and data spaces allow simultaneous access to program instructions and data, providing the
high degree of parallelism. Two read operations and one write operation can be performed in a single cycle.
Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition,
data can be transferred between data and program spaces. Such parallelism supports a powerful set of
arithmetic, logic, and bit-manipulation operations that can be performed in a single machine cycle. In addition,
the 5402 includes the control mechanisms to manage interrupts, repeated operations, and function calls.
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77251−1443
3
TMS320VC5402
FIXED POINT DIGITAL SIGNAL PROCESSOR
SPRS079G − OCTOBER 1998 − REVISED OCTOBER 2008
description (continued)
TMS320VC5402 PGE PACKAGE†‡
(TOP VIEW)
NC
NC
CV DD
A9
A8
A7
A6
A5
A4
HD6
A3
A2
A1
A0
DVDD
HDS2
VSS
HDS1
NC
CVDD
HD5
D15
D14
D13
HD4
D12
D11
D10
D9
D8
D7
D6
DV DD
VSS
NC
A19
119
118
117
116
115
114
113
112
111
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
110
NC
NC
VSS
DVDD
A10
HD7
A11
A12
A13
A14
A15
NC
HAS
VSS
NC
CVDD
HCS
HR/W
READY
PS
DS
IS
R/W
MSTRB
IOSTRB
MSC
XF
HOLDA
IAQ
HOLD
BIO
MP/MC
DVDD
VSS
NC
NC
109
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
A18
A17
VSS
A16
D5
D4
D3
D2
D1
D0
RS
X2/CLKIN
X1
HD3
CLKOUT
VSS
HPIENA
CVDD
NC
TMS
TCK
TRST
TDI
TDO
EMU1/OFF
EMU0
TOUT0
HD2
NC
CLKMD3
CLKMD2
CLKMD1
VSS
DVDD
NC
NC
† NC = No internal connection
‡ DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O
pins and the core CPU.
The TMS320VC5402PGE (144-pin LQFP) package is footprint-compatible with the ’LC548, ’LC/VC549, and
’VC5410 devices.
4
NC
NC
HCNTL0
VSS
BCLKR0
BCLKR1
BFSR0
BFSR1
BDR0
HCNTL1
BDR1
BCLKX0
BCLKX1
VSS
HINT/TOUT1
CVDD
BFSX0
BFSX1
HRDY
DV DD
V SS
HD0
BDX0
BDX1
IACK
HBIL
NMI
INT0
INT1
INT2
INT3
CVDD
HD1
VSS
NC
NC
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77251−1443
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