January 2007
rev 0.2
3-Pin µP Voltage Supervisor
PCS809/PCS810
FEATURES
•
•
•
Ultra Low Supply Current 1µA(typ.)
Guaranteed Reset Valid to VCC=0.9V
Available in three Output Types: Open Drain
Active Low (PCS809N), Push-Pull Active Low
(PCS809), Push-Pull Active High (PCS810)
•
•
•
•
140ms Min. Power-On Reset Pulse Width
Internally Fixed Threshold 2.3V, 2.6V, 2.9V,
3.1V, 4.0V, 4.4V, and 4.6V
Tight Voltage Threshold Tolerance: 1.5%
Low profile Package: SOT-23-3
DESCRIPTION
PCS809/PCS810 are low-power microprocessor (µP)
supervisory circuits used to monitor power supplies in µP
and digital systems. They provide applications with
benefits of circuit reliability and low cost by eliminating
external components.
These devices perform as valid singles in applications with
VCC ranging from 6.0V down to 0.9V. The reset signal
lasts for a minimum period of 140ms whenever VCC
supply voltage falls below preset threshold. Both PCS809
and PCS810 were designed with a reset comparator to
help identify invalid signals, which last less than 140ms.
The only difference between them is that they have an
active-low RESET output and active-high RESET output,
respectively.
Low supply current (1µA) makes PCS809/PCS810 ideal
APPLICATIONS
•
•
•
•
Notebook Computers
Digital Still Cameras
PDAs
Critical Microprocessor Monitoring
RESET THRESHOLD
Suffix
Voltage(V)
L
4.6
M
4.4
J
4.0
T
3.1
S
2.9
R
2.6
P
2.3
for portable equipment. The devices are available in 3-
SOT-23 package
Typical Operating Circuit
VCC
VCC
PCS809
(PCS810)
RESET
(RESET)
VCC
µP
RESET
INPUT
GND
GND
Push-Pull Output
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200 Campbell, CA 95008
•
Tel: 408-879-9077
•
Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
January 2007
PCS809/PCS810
rev 0.2
Pin Diagram
GND
1
PCS809
(PCS810)
RESET (RESET)
2
3
VCC
Pin Description
Pin#
PCS809
1
PCS810
1
Pin Name
GND
Ground.
Description
RESET is asserted LOW if V
CC
falls below V
TH
. RESET remains LOW for atleast
2
-
RESET
140ms (T
RST
) once V
CC
exceeds the Threshold. In addition, RESET is active LOW
RESET is asserted HIGH if V
CC
falls below V
TH
. RESET remains HIGH for atleast
-
2
RESET
VCC
140ms (T
RST
) once V
CC
exceeds the threshold. In addition, RESET is active HIGH
Power supply input voltage (3.0V, 3.3V, 5.0V)
3
3
Block Diagrams
N-ch Open-Drain Type
RESET
Reset Generator
NMOS
VCC
R1
Bandgap
R2
GND
Push-Pull Type
VCC
R1
Bandgap
Reset Generator
RESET (RESET)
R2
GND
3-Pin
µP Voltage Supervisor
Notice: The information in this document is subject to change without notice.
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January 2007
PCS809/PCS810
rev 0.2
Detailed Description
RESET OUTPUT
µP
will be activated at a valid reset state. These
µP
supervisory circuits assert reset to prevent code execution
errors
during
power-up,
power-down,
or
brownout
BENEFITS
THRESHOLD
PCS809/810 with specified voltage as 5V±10% or
3V±10% are ideal for systems using a 5V±5% or 3V±5%
power supply. The reset is guaranteed to assert after the
power supply falls out of regulation, but before power
drops below the minimum specified operating voltage
range of the system ICs. The pre-trimmed thresholds are
reducing the range over which an undesirable reset may
occur.
OF
HIGHLY
ACCURATE
RESET
conditions.
RESET is guaranteed to be a logic low for
V
TH
>VCC>0.9V. Once VCC exceeds the reset threshold,
an internal timer keeps RESET low for the reset timeout
period; after this interval, RESET goes high.
If a brownout condition occurs (VCC drops below the reset
threshold), RESET goes low. Any time VCC goes below
the reset threshold, the internal timer resets to zero, and
RESET goes low. The internal timer is activated after VCC
returns above the reset threshold, and RESET remains
low for the reset timeout period.
Application Information
NEGATIVE-GOING VCC TRANSIENTS
In addition to issuing a reset to the
µP
during power-up,
power-down, and brownout conditions, PCS809 series are
relatively resistant to short-duration negative-going VCC
transient.
ENSURING A VALID RESET OUTPUT DOWN TO
VCC=0
When VCC falls below 0.9V, PCS809 RESET output no
longer sinks current; it becomes an open circuit. In this
case, high-impedance CMOS logic inputs connecting to
RESET can drift to undetermined voltages. Therefore,
PCS809/810 with CMOS is perfect for most applications of
INTERFACING TO
µP
WITH BIDIRECTIONAL RESET
PINS
The RESET output on the PCS809 is open drain, this
device interfaces easily with
µPs
that have bidirectional
reset pins. Connecting the
µP
supervisor’s RESET output
directly to the microcontroller’s RESET pin with a single
pull-up resistor allows either device to assert reset.
VCC below 0.9V. However in applications where RESET
must be valid down to 0V, adding a pull-down resistor to
RESET causes any leakage currents to flow to ground,
holding RESET low.
3-Pin
µP Voltage Supervisor
Notice: The information in this document is subject to change without notice.
3 of 8
January 2007
PCS809/PCS810
rev 0.2
Absolute Maximum Rating
Parameter
VCC
RESET,RESET
Input Current (VCC)
Output Current (RESET or RESET)
Continuous Power Dissipation (T
A
=+70°C)
Operating Junction Temperature Range
Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering) 10 sec
-65
-40
Min
0.3
0.3
Max
6.5
Vcc+0.3
20
20
320
+85
125
150
260
Unit
V
V
mA
mA
mW
°C
°C
°C
°C
Test Circuit
VCC
TEST CIRCUIT
VCC
0.1uF
RESET
(RESET)
GND
3-Pin
µP Voltage Supervisor
Notice: The information in this document is subject to change without notice.
4 of 8
January 2007
PCS809/PCS810
rev 0.2
Electrical Characteristics:
(Typical valves are at T
A
=+25°C unless otherwise specified.) (Note1)
Parameter
Opreating Voltage
Supply Current
Symbol
VCC
I
CC
Test Conditions
Min
0.9
Typ
Max
6
Unit
V
VCC= V
TH
+0.1V
P device
R device
S device
T device
J device
M device
L device
T
A
=+25°C
T
A
-40°C to +85°C
T
A
=+25°C
T
A
-40°C to +85°C
T
A
=+25°C
T
A
-40°C to +85°C
T
A
=+25°C
T
A
-40°C to +85°C
T
A
=+25°C
T
A
-40°C to +85°C
T
A
=+25°C
T
A
-40°C to +85°C
T
A
=+25°C
T
A
-40°C to +85°C
2.265
2.254
2.561
2.548
2.857
2.842
3.054
3.038
3.940
3.920
4.334
4.312
4.531
4.508
1
2.3
2.6
2.9
3.1
4.0
4.4
4.6
20
140
100
0.8VCC
230
3
2.335
2.346
2.639
2.652
2.944
2.958
3.147
3.162
4.060
4.080
4.466
4.488
4.669
4.692
μA
RESET threshold
V
TH
V
VCC to Reset Delay
Reset Active Timeout Period
RESET output Voltage
T
RD
T
RP
V
OH
V
OL
V
OH
V
OL
VCC=V
TH
to (V
TH
-0.1V), V
TH
=3.1V
VCC=V
TH (MAX)
T
A
=+25°C
T
A
-40°C to +85°C
μS
560
1030
0.2VCC
mS
VCC = V
TH
+0.1V,I
SOURECE
=1mA
VCC = V
TH
-0.1V,IS
INK
=1mA
VCC = V
TH
+0.1V,I
SOURECE
=1mA
VCC = V
TH
-0.1V,I
SINK
=1mA
A
RESET output Voltage
0.8VCC
0.2VCC
V
Note1: Specifications are production tested at T =25°C. Specifications over the -40°C to 85°C operating temperature range are assured
by design, characterization and correlation with Statistical Quality Controls (SQC).
Note 2: RESET output is for PCS809: RESET output for PCS810.
3-Pin
µP Voltage Supervisor
Notice: The information in this document is subject to change without notice.
5 of 8
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