DATA SHEET
MOS FIELD EFFECT TRANSISTOR
2SK3386
SWITCHING
N-CHANNEL POWER MOS FET
INDUSTRIAL USE
ORDERING INFORMATION
PART NUMBER
2SK3386
2SK3386-Z
PACKAGE
TO-251
TO-252
DESCRIPTION
The 2SK3386 is N-Channel MOS Field Effect Transistor
designed for high current switching applications.
FEATURES
•
Low On-state Resistance
5
5
R
DS(on)1
= 21 mΩ MAX. (V
GS
= 10 V, I
D
= 17 A)
R
DS(on)2
= 36 mΩ MAX. (V
GS
= 4.0 V, I
D
= 17 A)
•
Low C
iss
: C
iss
= 2100 pF TYP.
•
Built-in Gate Protection Diode
•
TO-251/TO-252 package
(TO-251)
ABSOLUTE MAXIMUM RATINGS (T
A
= 25 °C)
Drain to Source Voltage
Gate to Source Voltage
Drain Current (DC)
5
5
Drain Current (Pulse)
Note1
V
DSS
V
GSS
I
D(DC)
I
D(pulse)
P
T
P
T
T
ch
T
stg
Note2
Note2
60
±20
±34
±120
40
1.0
150
–55 to +150
28
78
V
V
A
A
W
W
°C
°C
A
mJ
(TO-252)
Total Power Dissipation (T
C
= 25°C)
Total Power Dissipation (T
A
= 25°C)
Channel Temperature
Storage Temperature
5
5
Single Avalanche Current
Single Avalanche Energy
I
AS
E
AS
Notes 1.
PW
≤
10
µ
s, Duty cycle
≤
1 %
2.
Starting T
ch
= 25 °C, R
G
= 25
Ω,
V
GS
= 20 V
→
0 V
THERMAL RESISTANCE
5
Channel to Case
Channel to Ambient
R
th(ch-C)
R
th(ch-A)
3.13
125
°C/W
°C/W
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
D14471EJ1V0DS00 (1st edition)
Date Published January 2000 NS CP(K)
Printed in Japan
The mark
5
shows major revised points.
©
1999,2000
2SK3386
5
ELECTRICAL CHARACTERISTICS (T
A
= 25 °C)
CHARACTERISTICS
Drain to Source On-state Resistance
SYMBOL
R
DS(on)1
R
DS(on)2
Gate to Source Cut-off Voltage
Forward Transfer Admittance
Drain Leakage Current
Gate to Source Leakage Current
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
V
GS(off)
| y
fs
|
I
DSS
I
GSS
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
G
Q
GS
Q
GD
V
F(S-D)
t
rr
Q
rr
TEST CONDITIONS
V
GS
= 10 V, I
D
= 17 A
V
GS
= 4.0 V, I
D
= 17 A
V
DS
= 10 V, I
D
= 1 mA
V
DS
= 10 V, I
D
= 17 A
V
DS
= 60 V, V
GS
= 0 V
V
GS
= ±20 V, V
DS
= 0 V
V
DS
= 10 V
V
GS
= 0 V
f = 1 MHz
I
D
= 17 A
V
GS(on)
= 10 V
V
DD
= 30 V
R
G
= 10
Ω
I
D
= 34 A
V
DD
= 48 V
V
GS(on)
= 10 V
I
F
= 34 A, V
GS
= 0 V
I
F
= 34 A, V
GS
= 0 V
di/dt = 100 A/
µ
s
2100
340
170
32
310
98
100
39
7.0
12
0.87
46
84
1.5
10
MIN.
TYP.
17
25
2.0
19
10
±10
MAX.
21
36
2.5
UNIT
mΩ
mΩ
V
S
µ
A
µ
A
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
R
G
= 25
Ω
PG.
V
GS
= 20
→
0 V
BV
DSS
V
DS
V
GS
0
50
Ω
L
V
DD
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
R
L
PG.
R
G
V
DD
I
D
90 %
90 %
V
GS
V
GS
Wave Form
0
10 %
V
GS
(on)
90 %
I
AS
I
D
V
DD
I
D
I
D
Wave Form
0 10 %
10 %
τ
τ
= 1
µ
s
Duty Cycle
≤
1 %
t
d(on)
t
on
t
r
t
d(off)
t
off
t
f
Starting T
ch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
I
G
= 2 mA
50
Ω
R
L
V
DD
PG.
2
Data Sheet D14471EJ1V0DS00
2SK3386
•
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
•
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consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
•
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rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
•
Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
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of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
•
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the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
•
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"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
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equipment and industrial robots
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systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
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The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
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M7 98. 8