Galileo
Technology, Inc.
FEATURES
Single-Chip
System Controller
GT-32011
Rev. 2, July 95
Preliminary
NOTE: Always contact Galileo Technology for
possible updates before starting a design.
• Single Chip System Controller for the IDT R3051 fam-
ily of processors
• Features facilitate the implementation of high-perfor-
mance embedded control systems
• 16Mhz - 33Mhz CPU interface to: R3041/51/52/71/81
• DRAM Controller
1 - 40 MB directly
Device depth supported: 256K - 4M
1 - 3 banks directly
Non-interleave
• ROM Controller
1 - 20MB
Address-space support bank size: 1- 8MB
Support for standard and burst ROMs
Support for interleave or non interleave
• Direct Interface to External Agent/Coprocessor
• I/O Bus follows 8/16 Intel 80186 style
• I/O Controller
Two 8-bit and two 16-bit external channels
DMA and non-DMA access for the 8-bit channels
8-32 packing and 32-8 unpacking logic for DMA
access
Round robin arbitration
Programmable timing for I/O and control signals
Big and little endian support
16-32 packing and 32-16 unpacking for CPU/ Exter-
nal Co-processor accesses
• PCMCIA Support
Through 16-bit I/O bus, using simple glue logic
16-bit to 32-bit packing and 32-bit to 16-bit unpacking
Big and little endian support
256MB address space dedicated for 2 PCMCIA slots
• Parallel Port
Supports control for reading and writing from a 16-bit
parallel port
• Centronics Interface
Bi-directional Centronics, compliant with IEEE1284
Supports DMA and CPU controlled transfers
Supports the following modes:
Compatible; Nibble; Byte; ECP; EPP
• Interrupt Controller
6 external level interrupts (through the PIO pins)
10 internal interrupts
Individual interrupt mask capability, enabling polling
or interrupt-driven systems
• General Purpose I/O
Six programmable Input (interrupts) or Output pins
• 24-bit Timer/Counter
• In-circuit testing capability
• Packaged in a 160-pin PQFP
DRAM
Non I/L
1 - 40MB
GT-32011
System Controller
Parallel
Port
Control
16-bit Parallel
Port
ROM
I/L
or
Non I/L
1-20MB
DRAM
Control
3 C hannel D M A
CPU
R3041
R3051
R3052
R3071
R3081
16-33MHz
ROM
Control
System
Arbiter
CPU
Interface
16-bit
I/O Bus
Peripherals:
SCSI, Enet,
PCMCIA, etc.
Bidirectional
Centronics
IEEE1284
Modes:
Compatible
Nibble
Byte
ECP
EPP
External
Agent or
Co-
Processor
Co-Processor
DMA Interface
Interrupt
24-bit
Programmable
Controller Timer/Counter
I/O
eg.
Control Panel
1735 N. First St. #308, San Jose, CA 95112, Tel (408)451-1400, Fax (408)451-1404
1
GT-32011 Single Chip System Controller
Galileo
Technology, Inc.
OVERVIEW
The GT-32011 is a single chip System Controller
designed to complement IDT’s R3051 family of 32-bit
embedded processors. It has all the features necessary
to implement high-performance, high-quality, embedded
controllers. The GT-32011 is oriented towards data com-
munications equipment, telecommunications equip-
ment, office automation equipment, industrial and
medical instrumentation, and industrial controllers.
The GT-32011 can move large amounts of data quickly
without the need for processor intervention. It also
achieves a significant reduction in system cost by its high
level of integration. Additional savings come from the
architecture of the I/O controller, which allows for the uti-
lization of low cost peripheral components (disk control-
ler, network controller, etc.), while attaining the higher
level of performance only associated with costlier com-
ponents.
Some of the architectural characteristics that result in
very high performance include:
- incorporating a tightly coupled interface to a specific
RISC processor architecture;
- minimizing latency to critical resources;
- partitioning the system in a balanced way to attain
efficient use of shared resources;
- enabling several simultaneous operations in the sys-
tem.
The GT-32011 is ideal for modular design of embedded
control systems through a high level of programmability,
and by incorporating the control logic for an industry
standard interface to peripherals. This gives OEMs the
ability to offer several products from the same basic
design, as well as the ability to upgrade systems in the
field.
2
Galileo
Technology, Inc.
GT-32011 Single Chip System Controller
1
1.1
PIN INFORMATION
Logic Symbol
PIO
ROMCS(2:0)*
ROMOE*
DRAM
IODATA(15:0)
DMAREQ(1:0)
IOCS(1:0)*
IOGPCS(1:0)*
IOBE(1:0)*
IOA1
IORD*
IOWR*
DMAACK(1:0)*
IOWAIT*
DWR*
CAS(3:0)*
RAS(2:0)*
DADR(10:0)
PIO(5:0)
I/O Bus
Parallel
Port Control
ROM
PSTROBE*
POE*
OEMAD*
Buffer
Control
Bi-directional
Centronics
IEEE 1284
Misc.
CPU
Interface
External
Agent/Coprocessor
Interface
SYSCLK
TEST
RESET
VDD
VSS
CFAULT*
CACK*
CWOE*
CSELECT
CPERROR
CAUTOFD*
CROE*
CWSTROBE
CBUSY
CRSTROBE
CSTROBE*
CINIT*
CSELECTIN*
AD(31:0)
ADDR(3:2)
BURST*
ALE
RD*
WR*
ACK*
RDCEN*
BUSREQ*
BUSGNT*
INT*
DATAEN*
Fig. 1.1 : Logic Symbol
EADOE*
EADDIR*
EDTACK*
EDS*
EBREQ*
EBGNT*
EAS*
ECS*
EAACK*
EATOE*
3
GT-32011 Single Chip System Controller
Galileo
Technology, Inc.
1.2
Pin Assignment Table
Pull Up/
Pull Dn
Pin Name
CPU Interface
A/D[31:0]
Type
Drive
Description
P.U.
I/O
8mA
Address/Data:
Multiplexed address and data bus.
In the Address phase: A/D[31:4] are address, A/D[3:0] are Byte
Enable[3:0]. During Coprocessor Master cycles, A/D[3:2] contain
address bits 3 and 2, and not Byte Enables.
In the Data
phase: Data[31:0]
ADDR[3:2]
BURST*
P.U.
P.U.
I/O
I/O
4mA
2mA
Non Multiplexed Address:
Connected to the CPU ADDR[3:2].
In DMA cycles the GT-32011 drives these lines.
Burst Transfer:
Used only during read cycles, the BURST signal
indicates that the current bus read is requesting a block of four
continuous words from memory. The pin connects to the CPU’s
BURST/WRNEAR* signal. In DMA cycles the GT-32011 drives
this signal HIGH.
Address Latch Enable:
Used by the CPU to indicate that the
A/D bus contains valid address information for the bus transac-
tion. During Coprocessor DMA cycles, the GT-32011 asserts
ALE to capture the address supplied by the Coprocessor.
System Clock:
Connected directly to the CPU SYSCLK* output.
Read:
Indicates a read access by the CPU. In DMA cycles the
GT-32011 drives the signal HIGH.
Write:
Indicates a write access by the CPU or the Coprocessor.
In a non-Coprocessor DMA cycle the GT-32011 drives this sig-
nal HIGH.
Acknowledge:
Indicates that the memory system has suffi-
ciently processed the bus transaction i.e. that the CPU may
either terminate a write cycle or process read data.
Read Buffer Clock Enable:
Indicates to the CPU that there is
valid data on the A/D bus.
Bus Request:
The GT-32011 requests the CPU bus which is
required for I/O and Coprocessor DMA’s.
Bus Grant:
Indicates that the CPU has relinquished the bus.
Interrupt:
“OR’s” the internal and external interrupt sources.
Data Enable:
indicates the data phase in CPU read cycles. In
DMA the GT-32011 asserts DATAEN when the ROM/DRAM
drives data onto A/D[31:0].
ROM Chip Select:
Select one of the 3 ROM banks. They can be
connected to the ROM’s Chip Select or Output Enable.
ROMCS[2] is connected to the boot ROM, with a starting physi-
cal address 0x1fc00000.
ALE
P.D.
I/O
4mA
SYSCLK
RD*
WR*
P.U.
P.U.
I
I/O
I/O
2mA
2mA
ACK*
O
2mA
RDCEN*
BUSREQ*
BUSGNT*
INT*
DATAEN*
O
O
I
O
I/O
2mA
2mA
2mA
4mA
ROM
ROMCS[2:0]*
O
4mA
4
Galileo
Technology, Inc.
GT-32011 Single Chip System Controller
Pin Name
ROMOE*
Pull Up/
Pull Dn
Type
O
Drive
4mA
Description
ROM Output Enable:
Asserted when there is an access to any
of the ROM banks. Used to output- enable the ROM data in sys-
tems where there is a buffer between ROM and DRAM data bus;
eg. when using an interleaved ROM configuration.
DRAM Address:
Multiplexed row and column address con-
nected to the DRAM address.
Row Adress Select:
Supports up to three banks of DRAM, con-
nected to the RAS inputs of the DRAMs.
Column Address Select:
Connects a CAS to each of the four
bytes in every bank.
DRAM Write:
Connects to the write pin of each of the DRAMs.
DRAM
DADR[10:0]
RAS[2:0]*
CAS[3:0]*
DWR*
Coprocessor/
External Agent
Interface
EBREQ*
EBGNT*
P.U.
I
O
2mA
Ext. Agent Bus Request:
An Ext. Agent bus request to make
system resource access in master mode.
Ext. Agent Bus Grant:
The GT-32011 asserts EBGNT* to grant
the CPU bus to the Ext. Agent. Once the EBGNT* is asserted, it
remains so until EBREQ* is deasserted.
Ext. Agent Address Strobe:
Master Mode -The external agent indicates that it drives valid
data on the A/D bus.
Slave mode - The GT-32011 indicates that it drives valid data on
the A/D bus.
EDS*
O
2mA
Ext. Agent Data Strobe:
Master mode - during Write indicates that there is valid data on
the A/D bus. During Read indicates a request for data.
Slave mode - the GT-32011 drives EDS* to indicate that it is
ready to accept data during reads or that valid data is available
during writes on the A/D bus.
EDTACK*
P.U.
I/O
2mA
Ext. Agent Data acknowledge:
Master mode - The GT-32011 asserts EDTACK* to indicate that it
is receiving or driving the requested data to/from the A/D bus.
Slave mode - The Ext. Agent asserts EDTACK* to signal that it
has supplied or received data on its bus.
EAACK*
O
2mA
Ext. Agent Address Acknowledge:
The GT-32011 asserts
EAACK* one clock after asserting ALE for the Ext. Agent. This
insures that the Ext. Agent continues driving the address until
latched by the system.
Ext. Agent Chip Select:
When the CPU accesses the Ext.
Agent, the GT-32011 asserts ECS*. It is active one clock before
GT-32011 asserts EAS*.
O
O
O
O
8ma
4mA
4mA
12ma
EAS*
P.U.
I/O
2mA
ECS*
O
2mA
5
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