2SK3349
Silicon N Channel MOS FET
High Speed Switching
ADE-208-804 (Z)
1st.Edition.
June 1999
Features
•
Low on-resistance
R
DS
= 2.8
Ω
typ. (at V
GS
= 4 V , I
D
= 25 mA)
R
DS
= 4.8
Ω
typ. (at V
GS
= 2.5 V , I
D
= 10 mA)
•
2.5 V gate drive device
•
Small package (SMPAK)
Outline
SMPAK
3
1
2
D
G
1. Source
2. Gate
3. Drain
S
2SK3349
Absolute Maximum Ratings
(Ta = 25°C)
Item
Drain to source voltage
Gate to source voltage
Drain current
Drain peak current
Body-drain diode reverse drain current
Channel dissipation
Channel temperature
Storage temperature
Note:
Symbol
V
DSS
V
GSS
I
D
I
D(pulse)Note1
I
DR
Pch
Note 2
Tch
Tstg
Ratings
20
±10
50
200
50
100
150
–55 to +150
Unit
V
V
mA
mA
mA
mW
°C
°C
1. PW
≤
10
µs,
duty cycle
≤
1%
2. Value on the alumina ceramic board (12.5x20x0.7 mm)
Electrical Characteristics
(Ta = 25°C)
Item
Drain to source breakdown
voltage
Gate to source breakdown
voltage
Gate to source leak current
Zero gate voltege drain
current
Symbol
V
(BR)DSS
V
(BR)GSS
I
GSS
I
DSS
Min
20
±10
—
—
0.8
—
—
56
—
—
—
—
—
—
—
Typ
—
—
—
—
—
2.8
4.8
85
6
7
1.2
120
450
480
500
Max
—
—
±5
1
1.8
3.6
7.2
—
—
—
—
—
—
—
—
Unit
V
V
µA
µA
V
Ω
Ω
mS
pF
pF
pF
ns
ns
ns
ns
Test Conditions
I
D
= 100
µA,
V
GS
= 0
I
G
=
±100 µA,
V
DS
= 0
V
GS
=
±8
V, V
DS
= 0
V
DS
= 20 V, V
GS
= 0
I
D
= 10
µA,
V
DS
= 5 V
I
D
= 25 mA,V
GS
= 4 V
Note 3
I
D
= 10 mA,V
GS
= 2.5 V
Note 3
I
D
= 25 mA, V
DS
= 10 V
Note 3
Gate to source cutoff voltage V
GS(off)
Static drain to source on state R
DS(on)
resistance
Forward transfer admittance
Input capacitance
Output capacitance
R
DS(on)
|y
fs
|
Ciss
Coss
V
DS
= 10 V
V
GS
= 0
f = 1 MHz
I
D
= 25 mA, V
GS
= 4 V
R
L
= 400
Ω
Reverse transfer capacitance Crss
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Note:
3. Pulse test
4. Marking is DN
t
d(on)
t
r
t
d(off)
t
f
2
2SK3349
Main Characteristics
Power vs. Temperature Derating
200
*Pch (mW)
5
2
1.0
0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
Maximum Safe Operation Area
150
I
D
(A)
Channel Dissipation
10 µs
100 µs
1 ms
DC
Op
er
Drain Current
100
50
Operation in this area
is limited by RDS(on)
=
at
(1 10 m
ion
sh s
ot
)
PW
0
50
100
150
Ta ( °C)
200
0.0005
0.05 0.1 0.2
0.5 1.0 2
5
10 20
50
Ambient Temperature
Drain to Source Voltage
V
DS
(V)
*Value on the alumina ceramic boad.(12.5x20x0.7mm)
Value on the alumina ceramic boad.(12.5x20x0.7mm)
Typical Output Characteristics
5V
0.2
4V
I
D
(A)
Typical Transfer Characteristics
0.2
I
D
(A)
Pulse Test
3V
0.16
V
DS
= 10 V
Pulse Test
0.16
Drain Current
0.08
Drain Current
0.12
0.12
0.08
25 °C
0.04
75 °C
Tc = –25 °C
0.04
V
GS
= 2V
0
2
4
6
Drain to Source Voltage
8
V
DS
(V)
10
0
1
2
3
Gate to Source Voltage
4
V
GS
(V)
5
3
2SK3349
Drain to Source Satueation Voltage
vs. Gate to Source Voltage
1.0
Drain to Source Saturation Voltage
V
DS(on)
(V)
Pulse Test
Static Drain to Source on State
Resistance vs. Drain Current
50
Pulse Test
20
2.5 V
10
5
V
GS
= 4V
0.8
0.6
0.4
10m A
0.2
25m A
I
D
= 50mA
2
4
6
8
V
GS
(V)
10
Static Drain to Source on State Resistance
R
DS(on)
( )
2
1.0
0.5
0.01
0
Gate to Source Voltage
0.02
Drain Current
0.05
I
D
(A)
0.1
Static Drain to Source on State Resistance
R
DS(on)
( )
Forward Transfer Admittance |yfs| (mS)
10
Static Drain to Source on State
Resistance vs. Temperature
Forward Transfer Admittance
vs. Drain Current
0.5
0.2
0.1
0.05
75 °C
V
DS
= 10 V
Pulse Teat
Tc = –25 °C
8
I
D
= 25m A
6
V
GS
= 2.5 V
25 °C
10mA
4
10,25,50m A
4V
Pulse Test
0
40
80
Tc
120
(°C)
160
Case Temperature
0.02
0.01
0.005
0.001
2
0
–40
0.002
0.005
0.1
Drain Current I
D
(A)
4
2SK3349
Typical Capacitance
vs. Drain to Source Voltage
10
Switching Characteristics
10000
Ciss
Capacitance C (pF)
Switching Time t (ns)
Coss
1000
tr
tf
t d(off)
Crss
1.0
100
t d(on)
V
GS
= 2.5 V, V
DD
= 10 V
PW = 5 µs, duty < 1 %
0.02
Drain Current
0.05
I
D
(A)
0.1
0.1
0
V
GS
= 0
f = 1 MHz
4
8
12
16
Drain to Source Voltage V
DS
20
(V)
10
0.01
Reverse Drain Current
vs. Source to Drain Voltage
0.2
Reverse Drain Current I
DR
(A)
10 V
V
GS
= 0,-5V
5V
0.16
0.12
0.08
0.04
Pulse Test
0
0.4
0.8
1.2
1.6
V
SD
2.0
(V)
Source to Drain Voltage
5
FPGA/CPLD
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