INTEGRATED CIRCUITS
Xilinx has acquired the entire Philips CoolRunner Low Power
CPLD Product Family. For more technical or sales
information, please see: www.xilinx.com
XCR3032C
32 macrocell CPLD with enhanced clocking
Product specification
Supersedes data of 1998 Jul 23
IC27 Data Handbook
1998 Oct 06
Philips
Semiconductors
Philips Semiconductors
Product specification
32 macrocell CPLD with enhanced clocking
XCR3032C
Xilinx has acquired the entire Philips CoolRunner Low Power CPLD Product Family. For more technical
or sales information, please see: www.xilinx.com
FEATURES
DESCRIPTION
•
Industry’s first TotalCMOS™ PLD – both CMOS design and
process technologies
power and very high speed
•
Fast Zero Power (FZP™) design technique provides ultra-low
•
High speed pin-to-pin delays of 8ns
•
Ultra-low static power of less than 35µA
•
Dynamic power that is 70% lower at 50MHz than competing
•
100% routable with 100% utilization while all pins and all
•
Deterministic timing model that is extremely simple to use
•
Up to 6 clocks with programmable polarity at every macrocell
•
3.3 Volt, In-System Programmable (ISP) using a JTAG interface
–
–
–
–
–
On-chip supervoltage generation
ISP commands include: Enable, Erase, Program, Verify
Supported by multiple ISP programming platforms
4 pin JTAG interface (TCK, TMS, TDI, TDO)
JTAG commands include: Bypass, Idcode
macrocells are fixed
devices
The PZ3032C/PZ3032N CPLD (Complex Programmable Logic
Device) is a member of the Fast Zero Power (FZP™) family of
CPLDs from Philips Semiconductors. These devices combine high
speed and zero power in a 32 macrocell CPLD. With the FZP™
design technique, the PZ3032C/PZ3032N offers true pin-to-pin
speeds of 8ns, while simultaneously delivering power that is less
than 35µA at standby without the need for ‘turbo bits’ or other power
down schemes. By replacing conventional sense amplifier methods
for implementing product terms (a technique that has been used in
PLDs since the bipolar era) with a cascaded chain of pure CMOS
gates, the dynamic power is also substantially lower than any
competing CPLD—70% lower at 50MHz. These devices are the first
TotalCMOS™ PLDs, as they use both a CMOS process technology
and
the patented full CMOS FZP™ design technique. For 5V
applications, Philips also offers the high speed PZ5032C CPLD that
offers pin-to-pin speeds of 6ns.
The Philips FZP™ CPLDs introduce the new patent-pending XPLA™
(extended Programmable Logic Array) architecture. The XPLA™
architecture combines the best features of both PLA and PAL™ type
structures to deliver high speed and flexible logic allocation that
results in superior ability to make design changes with fixed pinouts.
The XPLA™ structure in each logic block provides a fast 8ns PAL™
path with 5 dedicated product terms per output. This PAL™ path is
joined by an additional PLA structure that deploys a pool of 32
product terms to a fully programmable OR array that can allocate
the PLA product terms to any output in the logic block. This
combination allows logic to be allocated efficiently throughout the
logic block and supports as many as 37 product terms on an output.
The speed with which logic is allocated from the PLA array to an
output is only 2.5ns, regardless of the number of PLA product terms
used, which results in worst case t
PD
’s of only 10.5ns from any pin
to any other pin. In addition, logic that is common to multiple outputs
can be placed on a single PLA product term and shared across
multiple outputs via the OR array, effectively increasing design
density.
The PZ3032C/PZ3032N CPLDs are supported by industry standard
CAE tools (Cadence, Exemplar Logic, Minc, Mentor, Synopsys,
Synario, Viewlogic, OrCAD), using text (Abel, VHDL, Verilog) and/or
schematic entry. Design verification uses industry standard
simulators for functional and timing simulation. Development is
supported on personal computer, Sparc, and HP platforms. Device
fitting uses either Minc or Philips Semiconductors-developed tools.
The PZ3032C/PZ3032N CPLD is reprogrammable using industry
standard device programmers from vendors such as Data I/O, BP
Microsystems, SMS, and others. The PZ3032C/PZ3032N also
includes an industry-standard, IEEE 1149.1, JTAG interface through
which In-System Programming (ISP) and reprogramming of the
device are supported.
•
Support for complex asynchronous clocking
•
Innovative XPLA™ architecture combines high speed with
•
1000 erase/program cycles guaranteed
•
20 years data retention guaranteed
•
Logic expandable to 37 product terms
•
PCI compliant
•
Advanced 0.5µ E
2
CMOS process
•
Security bit prevents unauthorized access
•
Design entry and verification using industry standard and Philips
•
Reprogrammable using industry standard device programmers
•
Innovative Control Term structure provides either sum terms or
product terms in each logic block for:
–
Programmable 3-State buffer
–
Asynchronous macrocell register preset/reset
–
Up to 2 asynchronous clocks
CAE tools
extreme flexibility
•
Programmable global 3-State pin facilitates ‘bed of nails’ testing
•
Available in both PLCC and TQFP packages
Table 1. PZ3032C/PZ3032N Features
PZ3032C/PZ3032N
Usable gates
Maximum inputs
Maximum I/Os
Number of macrocells
I/O macrocells
Buried macrocells
Propagation delay (ns)
Packages
1000
36
32
32
32
0
8.0
44-pin PLCC, 44-pin TQFP
without using logic resources
PAL is a registered trademark of Advanced Micro Devices, Inc.
1998 Oct 06
2
853–2081 20137
Philips Semiconductors
Product specification
32 macrocell CPLD with enhanced clocking
PZ3032C/PZ3032N
ORDERING INFORMATION
INFORMATION
ORDER CODE
PZ3032CS8A44
PZ3032CS10A44
PZ3032CS12A44
PZ3032NS10A44
PZ3032NS12A44
PZ3032CS8BC
PZ3032CS10BC
PZ3032CS12BC
PZ3032NS10BC
PZ3032NS12BC
DESCRIPTION
44-pin PLCC, 8ns t
PD
44-pin PLCC, 10ns t
PD
44-pin PLCC, 12ns t
PD
44-pin PLCC, 10ns t
PD
44-pin PLCC, 12ns t
PD
44-pin TQFP, 8ns t
PD
,
44-pin TQFP, 10ns t
PD
44-pin TQFP, 12ns t
PD
44-pin TQFP, 10ns t
PD
44-pin TQFP, 12ns t
PD
DESCRIPTION
Commercial temp range, 3.3 volt power supply,
±10%
Commercial temp range, 3.3 volt power supply,
±10%
Commercial temp range, 3.3 volt power supply,
±10%
Industrial temp range, 3.3 volt power supply,
±10%
Industrial temp range, 3.3 volt power supply,
±10%
Commercial temp range, 3.3 volt power supply,
±10%
Commercial temp range, 3.3 volt power supply,
±10%
Commercial temp range, 3.3 volt power supply,
±10%
Industrial temp range, 3.3 volt power supply,
±10%
Industrial temp range, 3.3 volt power supply,
±10%
DRAWING NUMBER
SOT187-2
SOT187-2
SOT187-2
SOT187-2
SOT187-2
SOT376-1
SOT376-1
SOT376-1
SOT376-1
SOT376-1
XPLA™ ARCHITECTURE
Figure 1 shows a high level block diagram of a 32 macrocell device
implementing the XPLA™ architecture. The XPLA™ architecture
consists of logic blocks that are interconnected by a Zero-power
Interconnect Array (ZIA). The ZIA is a virtual crosspoint switch. Each
logic block is essentially a 36V16 device with 36 inputs from the ZIA
and 16 macrocells. Each logic block also provides 32 ZIA feedback
paths from the macrocells and I/O pins.
From this point of view, this architecture looks like many other CPLD
architectures. What makes the CoolRunner™ family unique is what
is inside each logic block and the design technique used to
implement these logic blocks. The contents of the logic block will be
described next.
PRODUCT terms, and are used to control the preset/reset and
output enables of the 16 macrocells’ flip-flops. In addition, two of the
control terms can be used as clock signals (see Macrocell
Architecture section for details). The PAL array consists of a
programmable AND array with a fixed OR array, while the PLA array
consists of a programmable AND array with a programmable OR
array. The PAL array provides a high speed path through the array,
while the PLA array provides increased product term density.
Each macrocell has 5 dedicated product terms from the PAL array.
The pin-to-pin t
PD
of the PZ3032C/PZ3032N device through the PAL
array is 8ns. This performance is the fastest 3 volt CPLD available
today. If a macrocell needs more than 5 product terms, it simply gets
the additional product terms from the PLA array. The PLA array
consists of 32 product terms, which are available for use by all 16
macrocells. The additional propagation delay incurred by a
macrocell using 1 or all 32 PLA product terms is just 2.5ns. So the
total pin-to-pin t
PD
for the PZ3032C/PZ3032N using 6 to 37 product
terms is 10.5ns (8ns for the PAL + 2.5ns for the PLA).
Logic Block Architecture
Figure 2 illustrates the logic block architecture. Each logic block
contains control terms, a PAL array, a PLA array, and 16 macrocells.
The 6 control terms can individually be configured as either SUM or
MC0
MC1
I/O
MC15
16
16
LOGIC
BLOCK
36
ZIA
16
16
36
LOGIC
BLOCK
MC0
MC1
I/O
MC15
SP00550
Figure 1. Philips XPLA CPLD Architecture
1998 Oct 06
3
Philips Semiconductors
Product specification
32 macrocell CPLD with enhanced clocking
PZ3032C/PZ3032N
36 ZIA INPUTS
CONTROL
5
6
PAL
ARRAY
PLA
ARRAY
(32)
SP00435A
Figure 2. Philips XPLA Logic Block Architecture
1998 Oct 06
4
TO 16 MACROCELLS
Philips Semiconductors
Product specification
32 macrocell CPLD with enhanced clocking
PZ3032C/PZ3032N
Macrocell Architecture
Figure 3 shows the architecture of the macrocell used in the
CoolRunner™ PZ3032C/PZ3032N. The macrocell can be configured
as either a D or T type flip-flop or a combinatorial logic function. A
D-type flip-flop is generally more useful for implementing state
machines and data buffering while a T-type flip-flop is generally
more useful in implementing counters. Each of these flip-flops can
be clocked from any one of four sources. Two of the clock sources
(CLK0 and CLK1) are connected to low-skew, device-wide clock
networks designed to preserve the integrity of the clock signal by
reducing skew between rising and falling edges. Clock 0 (CLK0) is
designated as a “synchronous” clock and must be driven by an
external source. Clock 1 (CLK1) can be used as a “synchronous”
clock that is driven by an external source, or as an “asynchronous”
clock that is driven by a macrocell equation. Both CLK0 and CLK1
can clock the macrocell flip-flops on either the rising edge or the
falling edge of the clock signal. The other clock sources are two of
the six control terms (CT2 and CT3) provided in each logic block.
These clocks can be individually configured as either a PRODUCT
term or SUM term equation created from the 36 signals available
inside the logic block. The timing for asynchronous and control term
clocks is different in that the Tco time is extended by the amount of
time that it takes for the signal to propagate through the array and
reach the clock network, and the Tsu time is reduced. Please see
the app note titled “Understanding CoolRunner Clocking Options” for
more detail.
The six control terms of each logic block are used to control the
asynchronous Preset/Reset of the flip-flops and the enable/disable
of the output buffers in each macrocell. Control terms CT0 and CT1
are used to control the asynchronous Preset/Reset of the
macrocell’s flip-flop. Note that the Power-on Reset leaves all
macrocells in the “zero” state when power is properly applied, and
that the Preset/Reset feature for each macrocell can also be
disabled. Control terms CT2 and CT3 can be used as a clock signal
to the flip-flops of the macrocells, and as the Output Enable of the
macrocell’s output buffer. Control terms CT4 and CT5 can be used
to control the Output Enable of the macrocell’s output buffer. Having
four dedicated Output Enable control terms ensures that the
CoolRunner™ devices are PCI compliant. The output buffers can
also be always enabled or always disabled. All CoolRunner™
devices also provide a Global Tri-State (GTS) pin, which, when
enabled and pulled Low, will 3-State all the outputs of the device.
This pin is provided to support “In-Circuit Testing” or “Bed-of-Nails”
testing.
There are two feedback paths to the ZIA: one from the macrocell,
and one from the I/O pin. The ZIA feedback path before the output
buffer is the macrocell feedback path, while the ZIA feedback path
after the output buffer is the I/O pin feedback path. When the
macrocell is used as an output, the output buffer is enabled, and the
macrocell feedback path can be used to feedback the logic
implemented in the macrocell. When the I/O pin is used as an input,
the output buffer will be 3-Stated and the input signal will be fed into
the ZIA via the I/O feedback path, and the logic implemented in the
buried macrocell can be fed back to the ZIA via the macrocell
feedback path. It should be noted that unused inputs or I/Os should
be properly terminated (See the section on terminations in this data
sheet and the app note
Terminating Unused CoolRunner
™
I/O Pins).
TO ZIA
PAL
PLA
D/T
INIT
(P or R)
CT0
CT1
GND
Q
GTS
GND
CLK0
CLK0
CLK1
CLK1
CT4
CT5
V CC
GND
CT2
CT3
SP00551
Figure 3. PZ3032C/PZ3032N Macrocell Architecture
1998 Oct 06
5
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