DRAM
Austin Semiconductor, Inc.
1 MEG x 4 DRAM
Fast Page Mode DRAM
AVAILABLE AS MILITARY
SPECIFICATIONS
• SMD 5962-90847
• MIL-STD-883
DQ1
DQ2
WE\
RAS\
A9
A0
A1
A2
A3
Vcc
1
2
3
4
5
6
7
8
9
10
MT4C4001J
PIN
ASSIGNMENT
(Top View)
20-Pin SOJ (ECJ),
20-Pin LCC (ECN), &
20-Pin Gull Wing (ECG)
DQ1
DQ2
WE\
RAS\
A9
1
2
3
4
5
26
25
24
23
22
Vss
DQ4
DQ3
CAS\
OE\
20-Pin DIP (C, CN)
FEATURES
• Industry standard x4 pinout, timing, functions, and
packages
• High-performance, CMOS silicon-gate process
• Single +5V±10% power supply
• Low-power, 2.5mW standby; 300mW active, typical
• All inputs, outputs, and clocks are fully TTL and CMOS
compatible
• 1,024-cycle refresh distributed across 16ms
• Refresh modes: RAS\-ONLY, CAS\-BEFORE-RAS\
(CBR), and HIDDEN
• FAST PAGE MODE access cycle
• CBR with WE\ a HIGH (JEDEC test mode capable via
WCBR)
20
19
18
17
16
15
14
13
12
11
Vss
DQ4
DQ3
CAS\
OE\
A8
A7
A6
A5
A4
A0
A1
A2
A3
Vcc
9
10
11
12
13
18
17
16
15
14
A8
A7
A6
A5
A4
20-Pin DIP (CZ)
OE\ 1
DQ3 3
Vss
5
2 CAS\
4 DQ4
6 DQ1
8 WE\
10 A9
12 A1
14 A3
16 A4
18 A6
20 A8
DQ2 7
RAS\
9
A0 11
A2 13
Vcc 15
A5 17
A7 19
OPTIONS
• Timing
70ns access
80ns access
100ns access
120ns access
• Packages
Ceramic DIP (300 mil)
Ceramic DIP (400 mil)
Ceramic LCC*
Ceramic ZIP
Ceramic SOJ
Ceramic Gull Wing
MARKING
-7
-8
-10
-12
GENERAL DESCRIPTION
The MT4C4001J is a randomly accessed solid-state
memory containing 4,194,304 bits organized in a x4
configuration. During READ or WRITE cycles each bit is
uniquely addressed through the 20 address bits which are
entered 10 bits (A0-A9) at a time. RAS\ is used to latch the
first 10 bits and CAS\ the later 10 bits. A READ or WRITE
cycle is selected with the WE\ input. A logic HIGH on WE\
dictates READ mode while a logic LOW on WE\ dictates
WRITE mode. During a WRITE cycle, data-in (D) is latched
by the falling edge of WE\ or CAS\, whichever occurs last. If
WE\ goes LOW prior to CAS\ going LOW, the output pin(s)
remain open (High-Z) until the next CAS\ cycle. If WE\ goes
LOW after data reaches the output pin(s), Qs are activated and
retain the selected cell data as long as CAS\ remains low
(regardless of WE\ or RAS\). This LATE WE\ pulse results in
a READ-WRITE cycle. The four data inputs and four data
outputs are routed through four pins using common I/O and
pin direction is controlled by WE\ and OE\. FAST-PAGE-
MODE operations allow faster data operations (READ,
WRITE, or READ-MODIFY-WRITE) within a row address
(A0-A9) defined page boundary. The FAST PAGE MODE
(continued)
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
CN
C
ECN
CZ
ECJ
ECG
No.
No.
No.
No.
No.
No.
103
104
202
400
504
600
*NOTE:
If solder-dip and lead-attach is desired on LCC
packages, lead-attach must be done prior to the solder-
dip operation.
For more products and information
please visit our web site at
www.austinsemiconductor.com
MT4C4001J
Rev. 1.0 9/01
1
DRAM
Austin Semiconductor, Inc.
GENERAL DESCRIPTION (cont.)
cycle is always initiated with a row address strobe-in by RAS\
followed by a column address strobed-in by CAS\. CAS\ may
be toggled-in by holding RAS\ LOW and strobing-in different
column addresses, thus executing faster memory cycles.
Returning RAS\ HIGH terminates the FAST PAGE MODE
operation.
Returning RAS\ and CAS\ HIGH terminates a memory cycle
and decreases chip current to a reduced standby level. Also,
the chip is preconditioned for the next cycle during the RAS\
HIGH time. Memory cell data is retained in its corrected
stated by maintaining power and executing any RAS\ cycle
(READ, WRITE, RAS\-ONLY, CAS\-BEFORE-RAS\, or
HIDDEN REFRESH) so that all 1,024 combinations of RAS\
addresses (A0-A9) are executed at least every 16ms,
regardless of sequence. The CBR REFRESH cycle will
invoke the internal refresh counter for automatic RAS\
addressing.
MT4C4001J
FUNCTIONAL
WE\
CAS\
BLOCK
DIAGRAM
DATA IN
BUFFER
4
FAST PAGE MODE
DQ1
DQ2
DQ3
DQ4
*EARLY-WRITE
DETECTION CIRCUIT
DATA OUT
BUFFER
4
4
NO. 2 CLOCK
GENERATOR
OE\
10
10
10
ROW
DECODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
COLUMN
ADDRESS
BUFFER
REFRESH
CONTROLLER
10
COLUMN
DECODER
1024
4
Vcc
Vss
SENSE AMPLIFIERS
I/O GATING
1024 x 4
REFRESH
COUNTER
MEMORY
ARRAY
ROW ADDRESS
BUFFERS (10)
1024
10
RAS\
NO. 1 CLOCK
GENERATOR
NOTE:
WE\ LOW prior to CAS\ LOW, EW detection circuit output is a HIGH (EARLY-WRITE)
CAS\ LOW prior to WE\ LOW, EW detection circuit output is a LOW (LATE-WRITE)
MT4C4001J
Rev. 1.0 9/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
DRAM
Austin Semiconductor, Inc.
TRUTH TABLE
ADDRESSES
FUNCTION
Standby
READ
EARLY-WRITE
READ-WRITE
FAST-PAGE-MODE
READ
FAST-PAGE-MODE
EARLY-WRITE
FAST-PAGE-MODE
READ-WRITE
RAS\-ONLY REFRESH
HIDDEN REFRESH
RAS\
H
L
L
L
L
L
L
L
L
L
L
L H L
L H L
H L
CAS\
H X
L
L
L
H L
H L
H L
H L
H L
H L
H
L
L
L
DATA IN/OUT
DQ1-DQ4
High-Z
Data Out
Data In
Data Out/Data In
Data Out
Data Out
Data In
Data In
Data Out/Data In
Data Out/Data In
High-Z
Data Out
Data In
High-Z
MT4C4001J
1st Cycle
2nd Cycle
1st Cycle
2nd Cycle
1st Cycle
2nd Cycle
READ
WRITE
CAS\-BEFORE-RAS\ REFRESH
WE\
X
H
L
H L
H
H
L
L
H L
H L
X
H
L
H
OE\
X
L
X
L H
L
L
X
X
L H
L H
X
L
X
X
R
X
ROW
ROW
ROW
ROW
n/a
ROW
n/a
ROW
n/a
ROW
ROW
ROW
X
t
C
X
COL
COL
COL
COL
COL
COL
COL
COL
COL
n/a
COL
COL
X
t
MT4C4001J
Rev. 1.0 9/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
DRAM
Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Vss.................-1.0V to +7.0V
Storage Temperature.......................................-65
o
C to +150
o
C
Power Dissipation.................................................................1W
Short Circuit Output Current...........................................50mA
Lead Temperature (soldering 5 seconds).....................+270
o
C
MT4C4001J
*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation section of this specification is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(NOTES: 1, 3, 4, 6, 7) (-55°C < T
A
< 125°C; V
C
= 5V ±10%)
C
PARAMETER/CONDITION
Supply Voltage
Input High (Logic 1) Voltage, All Inputs
Input Low (Logic 0) Voltage, All Inputs
INPUT LEAKAGE CURRENT
Any Input 0V < V
IN
< 5.5V Vcc = 5.5V
(All other pints not under test = 0V)
OUTPUT LEAKAGE CURRENT
(Q is Disabled, 0V < V
OUT
< 5.5V) Vcc = 5.5V
OUTPUT LEVELS
Output High Voltage (I
OUT
= -5mA)
Output Low Voltage (I
OUT
= 4.2mA)
SYM
V
CC
V
IH
V
IL
I
I
MIN
4.5
2.4
-0.5
-5
MAX
5.5
V
CC
+0.5
0.8
5
UNITS
V
V
V
µA
NOTES
I
OZ
V
OH
V
OL
-5
2.4
5
µA
V
0.4
MAX
-8
-10
4
2
4
2
V
PARAMETER/CONDITION
STANDBY CURRENT (TTL)
(RAS\ = CAS\ = V
IH
)
STANDBY CURRENT (CMOS)
(RAS\ = CAS\ = V
CC
-0.2V; all other inputs = V
CC
-0.2V)
OPERATING CURRENT: Random READ/WRITE
Average Power-Supply Current
(RAS\, CAS\, Address Cycling: t
RC
= t
RC
(MIN))
OPERATING CURRENT: FAST PAGE MODE
Average Power-Supply Current
(RAS\ = V
IL
, CAS\, Address Cycling: t
PC
= t
PC
(MIN))
REFRESH CURRENT: RAS\-ONLY
Average Power-Supply Current
(RAS\ Cycling, CAS\ = V
IH
: t
RC
= t
RC
(MIN))
REFRESH CURRENT: CAS\-BEFORE-RAS\
Average Power-Supply Current
(RAS\, CAS\, Address Cycling: t
RC
= t
RC
(MIN))
SYM
I
CC1
I
CC2
-7
4
2
-12
4
2
UNITS NOTES
mA
mA
I
CC3
85
75
65
70
mA
3, 4
I
CC4
60
50
45
40
mA
3, 4
I
CC5
85
75
65
70
mA
3
I
CC6
85
75
65
70
mA
3, 5
MT4C4001J
Rev. 1.0 9/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
DRAM
Austin Semiconductor, Inc.
CAPACITANCE
PARAMETER
Input Capacitance: A0-A10
Input Capacitance: RAS\, CAS\, WE\, OE\
Input/Output Capacitance: DQ
SYM
C
I1
C
I2
C
IO
MIN
MAX
7
7
8
UNITS
pF
pF
pF
NOTES
2
2
2
MT4C4001J
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(NOTES: 6, 7, 8, 9, 10, 11, 12, 13) (-55°C < T
C
< 125°C; V
C
= 5V ±10%)
C
-7
PARAMETER
Random READ or WRITE cycle time
READ-WRITE cycle time
FAST-PAGE-MODE READ or WRITE cycle time
FAST-PAGE-MODE READ-WRITE cycle time
Access time from RAS\
Access time from CAS\
Access time from column address
Access time from CAS\ precharge
RAS\ pulse width
RAS\ pulse width (FAST PAGE MODE)
RAS\ hold time
RAS\ precharge time
CAS\ pulse width
CAS\ hold time
CAS\ precharge time
CAS\ precharge time (FAST PAGE MODE)
RAS\ to CAS\ delay time
CAS\ to RAS\ precharge time
Row address setup time
Row address hold time
RAS\ to column address delay time
Column address setup time
Column address hold time
Column address hold time (referenced to RAS\)
Column address to RAS\ lead time
Read command setup time
Read command hold time (referenced to CAS\)
Read command hold time (referenced to RAS\)
CAS\ to output in Low-Z
Output buffer turn-off delay
WE\ command setup time
SYM
t
RC
t
RWC
t
PC
t
PRWC
t
RAC
t
CAC
t
AA
t
CPA
t
RAS
t
RASP
t
RSH
t
RP
t
CAS
t
CSH
t
CPN
t
CP
t
RCD
t
CRP
t
ASR
t
RAH
t
RAD
t
ASC
t
CAH
t
AR
t
RAL
t
RCS
t
RCH
t
RRH
t
CLZ
t
OFF
t
WCS
70
70
20
50
20
70
10
10
20
5
0
10
15
0
15
50
35
0
0
0
0
0
0
20
35
50
10,000
MIN
130
180
40
90
70
20
35
35
10,000
100,000
80
80
20
60
20
80
10
10
20
5
0
10
15
0
15
60
40
0
0
0
0
0
0
20
40
60
10,000
MAX
MIN
150
200
45
90
80
20
40
40
10,000
100,000
100
100
25
70
25
100
12
12
25
5
0
15
20
0
20
70
50
0
0
0
0
0
0
20
50
75
10,000
-8
MAX
MIN
190
240
55
110
90
25
45
45
10,000
100,000
120
120
30
90
30
120
15
15
25
10
0
15
20
0
25
85
60
0
0
0
0
0
0
20
60
90
-10
MAX
MIN
220
255
70
140
120
30
60
60
100,000
100,000
-12
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
21, 27
19
19
18
17
16
14
15
NOTES
MT4C4001J
Rev. 1.0 9/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
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