TS83110
LOW POWER 10 BIT - 55 MSPS A/D CONVERTER
1. DESCRIPTION
The TS83110 is a monolithic sampling 10 bit A/D con-
verter combining integrated Track & Hold, internal refer-
ence and nap mode functions. Designed on a high
speed bipolar technology, the TS83110 uses innovative
architecture allowing to sample up to 55 MSPS while
maintaining low power consumption.
Digital inputs/outputs are TTL compatible but outputs
are also tristate and CMOS 3.3 V logic compatible.
2. MAIN FEATURES
H
Low power : 190 mW typ.
H
Single power supply : + 5 V.
H
2.5
±
0.5 volt single ended analog input.
H
Analog bandwidth : 120 MHz.
H
Undersampling capability.
H
Tristate TTL output / Compatible with CMOS 3.3 V
logic.
H
Nap mode (I
Nap
= 8 mA).
H
Wide sampling frequency range : 1 to 55 MSPS.
H
High dynamic performance :
- 8.5 bit at f
S
= 50 MSPS / f
IN
= 10 MHz.
- 8 bit at f
S
= 40 MSPS / f
IN
= 20 MHz (Nyquist).
H
C
IN
: 5 pF / C
load
: 10 pF max.
H
SFDR = 60 dB (typ) at F
S
= 50 MSPS / F
in
= 10 MHz.
H
Evaluation board available : TSEV83148/110.
3. APPLICATIONS
H
Imaging (medical, ultrasound, IR, RX, frame grabber,
tomography).
H
Instrumentation (oscilloscope, ATE).
H
Home office (fax, scanner, visioconference, video
board).
H
Communication (set-top boxes, receiver, base sta-
tion, wireless telephone).
H
Video (advanced television, multimedia application).
H
High energy physics.
H
Military and space applications.
4.
H
H
H
H
H
H
H
PACKAGING / SCREENING / RADIATION
28 pin SOIC plastic package.
28 CDFP ceramic package.
Civil temperature range : 0, +70°C (C suffix).
Industrial temperature range : –40, +85°C (V suffix).
Military temperature range : –55, +125°C (M suffix).
MIL-STD-883-C planned.
Radiation tolerant : 150 Krad(Si) total dose expected.
Z suffix
CDFP 28
Dual ceramic flat pack
- Gullwing shape (to be confirmed)
- Straight lead / tie bar available (ZT suffix)
S suffix
Plastic SOIC 28
August 1997
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TS83110
5. ABSOLUTE MAXIMUM RATINGS
(see note)
Parameter
Analog supply voltage
Digital supply voltage
Analog input voltage
Reference input voltage
Reference output current
Clock input voltage
Maximum difference between positive supplies
Digital input voltage
Digital output current
Junction temperature
Plastic package
Ceramic package
Storage temperature
Lead temperature (soldering 10 s)
Note :
Symbol
AV
CC
DV
CC
V
IN
V
REF
I
VOUT
CLK
DV
CC
to AV
CC
V
D
I
D
T
j
Value
GND to 6
GND to 6
GND to V
CC
GND to V
CC
3
GND to V
CC
0.5
GND to V
CC
4
Unit
V
V
V
V
mA
V
V
V
mA
°C
°C
°C
°C
+150
+165
T
stg
T
leads
–65 to +150
+300
Absolute maximum ratings are limiting values, to be applied individually, while other parameters are within specified
operating conditions.
Long exposure to maximum rating may affect device reliability.
6. HANDLING
ESD sensitivity > 1500 V (TBD).
Latch-up sensitivity : (TBD).
7. USER WARNING
The power supplies must be applied before all the other signals to prevent damage from occurring on the device.
8. RECOMMENDED CONDITIONS OF USE
Parameter
Analog supply voltage
Digital supply voltage
Analog input voltage
Reference input voltage
Clock input voltage
Load
Operating temperature range
Symbol
AV
CC
DV
CC
V
IN
V
REF
CLK
Cload
T
amb
Single LS latch
Civil :
”C” grade
Industrial : ”V” grade
Military : ”M” grade
Available from V
OUT
Comments
Min.
Typ.
5
5
2.5
±
0.5
2.5
TTL levels
5
0 to +70
–40 to +85
–55 to +125
50
10
Max.
Unit
V
V
V
V
V
pF
°C
Clock duty cycle
DC
%
Decoupling : Power supply and V
REF
must be decoupled with external 100 nF chip capacitors. Without this capacitor, dynamic char-
acteristics are significantly affected.
2/16
TS83110
9. ELECTRICAL OPERATING CHARACTERISTICS
DVcc = AV
CC
= 5 V ; Fs = 40 MSPS ; T
a
= 25°C (unless otherwise specified) ; V
REF
= 2.5 V
Parameter
RESOLUTION
DIGITAL INPUTS AND OUTPUTS
Logic compatibility
Digital inputs
- Logic ”0” voltage
- Logic ”1” voltage
- Input current (NAP, TS, CLK)
Digital outputs
- Logic ”0” voltage I
OL
= 2 mA
- Logic ”1” voltage I
OH
= 2 mA
- Output delay
Input capacitance
ANALOG INPUT
Voltage range
Input bias current
Input resistance
Input capacitance
Analog bandwidth
ANALOG OUTPUT
Output voltage reference (VOUT)
ACCURACY
Differential non linearity
FS = 10 MSPS ; Fin = 1 MHz
Integral non linearity
FS = 10 MSPS ; Fin = 1 MHz
Gain error
full
Gain error drift
Input offset voltage
p
g
full
Differential phase
Differential gain
Monotonicity and no missing codes
full
full
DNL
full
INL
full
0.7
0.9
1.6
2.4
±0.5
±1
±130
±4
±6
0.8
0.8
guaranteed
3/16
LSB
LSB
LSB
LSB
% FS
% FS
ppm/°C
mV
mV
°
%
V
OUT
2,4
2.5
2.6
V
V
IN
I
IN
R
IN
C
IN
Bw
2
250
10
5
120
3
V
mA
KW
pF
MHz
I/O
TTL
Symbol
T
amb
Test
level
Min.
Typ.
10
Max.
Unit
bits
V
IL
V
IH
I
IL
full
full
0
2
120
0.8
5
V
V
mA
V
OL
V
OH
TOD
C
CLK
full
full
0,1
2.4
6 ns
6
0.5
3.3
V
V
ns
pF
TS83110
Parameter
DYNAMIC CHARACTERISTICS
Transient response
V
in
= 1.9 Vpp
Symbol
T
amb
Test
level
Min.
Typ.
Max.
Unit
TR
ORT
F
S
F
S
SFDR
15
25
55
0.5
1
ns
ns
MSPS
MSPS
Overvoltage recovery time
Maximum clock frequency
Minimum clock frequency
Spurious Free Dynamic Range
F
S
= 50 MSPS ; F
IN
= 10 MHz
F
S
= 40 MSPS ; F
IN
= 20 MHz
Power Supply Rejection Ratio
Signal to noise ratio
F
S
= 50 MSPS, F
IN
= 10 MHz
F
S
= 40 MSPS, F
IN
= 20 MHz
Total harmonic distorsion
F
S
= 50 MSPS, F
IN
= 10 MHz
F
S
= 40 MSPS, F
IN
= 20 MHz
Signal to noise and distorsion ratio
F
S
= 50 MSPS, F
IN
= 10 MHz
F
S
= 40 MSPS, F
IN
= 20 MHz
Effective number of bits
F
S
= 50 MSPS, F
IN
= 10 MHz
F
S
= 40 MSPS, F
IN
= 20 MHz
Dual tone intermodulation
(Fin1 = 9.9 MHz@1/2 FS
(Fin2 = 10.1 MHz@1/2 FS)
Bit Error Rate
F
S
= 40 MSPS, F
IN
= 10 MHz
Output error >
±16
LSB
POWER REQUIREMENTS
Power supply
AVcc
DVcc
60
58
PSRR
SNR
54
51
THD
60
49
SINAD
53
47
ENOB
8.5
8
IMD
63
TBD
dB
dB
mV/V
dB
dB
dBc
dBc
dB
dB
bits
bits
dB
BER
10
–10
error/
sample
full
4.75
4.75
5
5
190
40
5.25
5.25
TBD
V
V
mW
mW
Power dissipation Normal mode
Nap mode
THERMAL RESISTANCES
SOIC 28 (plastic)
Junction to ambient
Junction to case
qJA
qJC
qJA
qJC
57
10
56
13
°C/W
°C/W
CDFP 28 (ceramic)Junction to ambient
Junction to case
Note :
Analog input range (offset only) can be adjusted using V
REF
input : V
REF
– 0.5 V < V
IN
< V
REF
+ 0.5 V ; 2.3 V <V
REF
< 3.3 V
4/16
TS83110
EXPLANATION OF TEST LEVELS
I
II
III
IV
V
VI
100% production tested at +25°C
100 % production tested at +25°C, and sample tested at specified temperatures
(AC testing done on sample)
Sample tested only
Parameter is guaranteed by design and characterization testing
Parameter is a typical value only
All devices are 100 % production tested at +25°C. 100 % production tested at temperature
extremes for military temperature devices, guaranteed by design and characterization testing for
(civil) and industrial devices.
100 % probe tested on wafer at +25°C
D
Only MIN and MAX values are tested and guaranted (typical values are not tested).
10. TS83110 BLOCK DIAGRAM
16
V
IN
2
T/H
V
REF
AMP.
BANK
16
4 BIT
COARSE
ADC
2
INTERPOLATION
STAGES
V
OUT
BANDGAP
REF
2.5 V
4+1
6
CLK
CLOCK
BUFFER
DECODE AND OVERRANGE
LOGIC
1
10
INTERNAL
BIASING
TS
CONTROL
OUTPUT BUFFERS
10
NAP
TS
Over Range
Digital Outputs
TS is inactivated when tied at GND. If TS is connected to VCC, output data will be set in high impedance mode.
NAP is inactivated when tied at GND. If NAP is connected to VCC, bandgap references will be inhibited, digital output will
be in high impedance mode (TS) and power consumption will be lower than 8 mA.
5/16
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