16 MEG: x4, x8
SDRAM
SYNCHRONOUS
DRAM
FEATURES
• PC100-compliant; includes CONCURRENT AUTO
PRECHARGE
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can be
changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge and Auto Refresh Modes
• Self Refresh Mode
• 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
• Longer lead TSOP for improved reliability (OCPL*)
• One- and two-clock WRITE recovery (
t
WR) versions
MT48LC4M4A1/A2 S - 2 Meg x 4 x 2 banks
MT48LC2M8A1/A2 S - 1 Meg x 8 x 2 banks
For the latest data sheet revisions, please refer to the
Micron Web site:
www.micron.com/datasheets.
PIN ASSIGNMENT (Top View)
44-Pin TSOP
x4
-
NC
x8
V
DD
DQ0
VssQ
DQ1
V
DD
Q
DQ2
VssQ
DQ3
V
DD
Q
NC
NC
WE#
CAS#
RAS#
CS#
BA
A10
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
x8
Vss
DQ7
VssQ
DQ6
V
DD
Q
DQ5
VssQ
DQ4
V
DD
Q
NC
NC
DQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
Vss
x4
-
NC
-
DQ0
-
DQ3
-
NC
-
NC
-
DQ1
-
DQ2
OPTIONS
• Configurations
4 Meg x 4 (2 Meg x 4 x 2 banks)
2 Meg x 8 (1 Meg x 8 x 2 banks)
MARKING
4M4
2M8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
• WRITE Recovery (
t
WR/
t
DPL)
t
WR = 1 CLK
A1
t
WR = 2 CLK (Contact factory for availability.)A2
• Plastic Package - OCPL*
44-pin TSOP (400 mil)
• Timing (Cycle Time)
8ns;
t
AC = 6ns @ CL = 3
10ns;
t
AC = 9ns @ CL = 2
NOTE:
The # symbol indicates signal is active LOW. A dash
(-) indicates x4 pin function is same as x8 pin
function.
TG
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
4 MEG x 4
2 MEG x 8
2 Meg x 4 x 2 banks 1 Meg x 8 x 2 banks
4K
4K
2K (A0-A10)
2K (A0-A10)
2 (BA)
1 (BA)
1K (A0-A9)
512 (A0-A8)
-8B
-10
NOTE:
The 16Mb SDRAM base number differentiates the
offerings in two places: MT48LC2M8A1 S. The fourth
field distinguishes the architecture offering: 4M4
designates 4 Meg x 4, and 2M8 designates 2 Meg x 8.
The fifth field distinguishes the WRITE recovery
offering: A1 designates one CLK and A2 designates two
CLKs.
Part Number Example:
KEY TIMING PARAMETERS
SPEED
GRADE
-8B
-10
-8B
-10
CLOCK
ACCESS TIME
SETUP
FREQUENCY CL = 2** CL = 3** TIME
125 MHz
100 MHz
83 MHz
66 MHz
–
–
9ns
9ns
6ns
7.5ns
–
–
2ns
3ns
2ns
3ns
HOLD
TIME
1ns
1ns
1ns
1ns
MT48LC2M8A1TG-10 S
16Mb (x4/x8) SDRAM PART NUMBERS
PART NUMBER
MT48LC4M4A1TG S
MT48LC2M8A1TG S
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
ARCHITECTURE
4 Meg x 4 (
t
WR = 1 CLK)
2 Meg x 8 (
t
WR = 1 CLK)
* Off-center parting line
**CL = CAS (READ) latency
1
©1998, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
16 MEG: x4, x8
SDRAM
GENERAL DESCRIPTION
The Micron 16Mb SDRAM is a high-speed CMOS,
dynamic random-access memory containing 16,777,216
bits. It is internally configured as a dual memory array
(the 4 Meg x 4 is a dual 2 Meg x 4, and the 2 Meg x 8 is a dual
1 Meg x 8) with a synchronous interface (all signals are
registered on the positive edge of the clock signal, CLK).
Each of the two internal banks is organized with 2,048
rows and either 1,024 columns by 4 bits (4 Meg x 4) or 512
columns by 8 bits (2 Meg x 8).
Read and write accesses to the SDRAM are burst ori-
ented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an AC-
TIVE command, which is then followed by a READ or
WRITE command. The address bits registered coinci-
dent with the ACTIVE command are used to select the
bank and row to be accessed (BA selects the bank, A0-A10
select the row). The address bits registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
The SDRAM provides for programmable READ or
WRITE burst lengths of 1, 2, 4, or 8 locations, or the full
page, with a burst terminate option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst
sequence.
The Micron 16Mb SDRAM uses an internal pipelined
architecture to achieve high-speed operation. This ar-
chitecture is compatible with the 2n rule of prefetch
architectures, but it also allows the column address to be
changed on every clock cycle to achieve a high-speed,
fully random access. Precharging one bank while access-
ing the alternate bank will hide the PRECHARGE cycles
and provide seamless, high-speed, random-access op-
eration.
The Micron 16Mb SDRAM is designed to operate in
3.3V, low-power memory systems. An auto refresh mode
is provided, along with a power-saving, power-down
mode. All inputs and outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM operat-
ing performance, including the ability to synchronously
burst data at a high data rate with automatic column-
address generation, the ability to interleave between in-
ternal banks in order to hide precharge time, and the
capability to randomly change column addresses on each
clock cycle during a burst access.
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
TABLE OF CONTENTS
Functional Block Diagram - 4 Meg x 4 ........................
Functional Block Diagram - 2 Meg x 8 ........................
Pin Descriptions ............................................................
Functional Description
................................................
Initialization .............................................................
Register Definitions .................................................
Mode Register .....................................................
Burst Length ..................................................
Burst Type .....................................................
CAS Latency ..................................................
Operating Mode ............................................
Write Burst Mode .........................................
Commands
.....................................................................
Truth Table 1 (Commands and DQM Operation)
.......
Command Inhibit ..............................................
No Operation (NOP) ..........................................
Load Mode Register ...........................................
Active ...................................................................
Read .....................................................................
Write ....................................................................
Precharge ............................................................
Auto Precharge ...................................................
Burst Terminate .................................................
Auto Refresh .......................................................
Self Refresh .........................................................
Operation
.......................................................................
Bank/Row Activation .........................................
Reads ...................................................................
Writes ..................................................................
Precharge ............................................................
Power-Down .......................................................
4
5
6
7
7
7
7
7
7
9
9
9
10
10
11
11
11
11
11
11
11
11
11
12
12
13
13
14
20
22
22
Clock Suspend ....................................................
Burst Read/Single Write ....................................
Concurrent Auto Precharge ..............................
Truth Table 2 (CKE)
.................................................
Truth Table 3 (Current State)
....................................
Truth Table 4 (Current State)
....................................
Absolute Maximum Ratings .........................................
DC Electrical Characteristics and Operating Conditions .
I
CC
Operating Conditions and Maximum Limits ........
Capacitance ....................................................................
Timing Waveforms
Initialize and Load Mode Register .........................
Power-Down Mode ..................................................
Clock Suspend Mode ...............................................
Auto Refresh Mode ..................................................
Self Refresh Mode ....................................................
Reads
Read - Without Auto Precharge ........................
Read - With Auto Precharge ..............................
Alternating Bank Read Accesses .......................
Read - Full-Page Burst .......................................
Read - DQM Operation ......................................
Writes
Write - Without Auto Precharge .......................
Write - With Auto Precharge .............................
Alternating Bank Write Accesses ......................
Write - Full-Page Burst ......................................
Write - DQM Operation .....................................
23
23
24
26
27
29
31
31
31
32
AC Electrical Characteristics (Timing Table)
............ 32
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
FUNCTIONAL BLOCK DIAGRAM
4 Meg x 4 SDRAM
ROW
DECODER
11
ROW-
ADDRESS
LATCH
11
2,048
BANK 0
MEMORY
ARRAY
(2,048 x 1,024 x 4)
CKE
CLK
COMMAND
DECODE
DQM
CONTROL
LOGIC
1,024 (x4)
CS#
WE#
CAS#
RAS#
SENSE AMPLIFIERS
I/O GATING
DQM MASK LOGIC
MODE REGISTER
1,024
COLUMN-
ADDRESS BUFFER
BURST COUNTER
4
DATA
OUTPUT
REGISTER
12
10
COLUMN-
ADDRESS LATCH
10
COLUMN
DECODER
4
4
DATA
INPUT
8
REGISTER
DQ0 -
DQ3
1,024
A0-A10, BA
12
ADDRESS
REGISTER
REFRESH
CONTROLLER
SENSE AMPLIFIERS
I/O GATING
DQM MASK LOGIC
11
ROW-
ADDRESS
MUX
REFRESH
COUNTER
1,024 (x4)
11
ROW
DECODER
11
ROW-
ADDRESS
LATCH
11
2,048
BANK 1
MEMORY
ARRAY
(2,048 x 1,024 x 4)
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
FUNCTIONAL BLOCK DIAGRAM
2 Meg x 8 SDRAM
ROW
DECODER
11
ROW-
ADDRESS
LATCH
11
2,048
BANK 0
MEMORY
ARRAY
(2,048 x 512 x 8)
CKE
CLK
COMMAND
DECODE
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
512 (x8)
DQM
SENSE AMPLIFIERS
I/O GATING
DQM MASK LOGIC
MODE REGISTER
512
COLUMN-
ADDRESS BUFFER
BURST COUNTER
8
DATA
OUTPUT
REGISTER
12
9
COLUMN-
ADDRESS LATCH
9
COLUMN
DECODER
8
8
DATA
INPUT
8
REGISTER
DQ0 -
DQ7
512
A0-A10, BA
12
ADDRESS
REGISTER
REFRESH
CONTROLLER
SENSE AMPLIFIERS
I/O GATING
DQM MASK LOGIC
11
ROW-
ADDRESS
MUX
REFRESH
COUNTER
512 (x8)
11
ROW
DECODER
11
ROW-
ADDRESS
LATCH
11
2,048
BANK 1
MEMORY
ARRAY
(2,048 x 512 x 8)
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
