HD74ALVCH16721
3.3-V 20-bit Flip Flops with 3-state Outputs
ADE-205-139B (Z)
3rd. Edition
December 1999
Description
The HD74ALVCH16721’s twenty flip flops are edge triggered D-type flip flops with qualified clock
storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs,
provided that the clock enable (CLKEN) input is low. If
CLKEN
is high, no data is stored. A buffered
output enable (OE) input can be used to place the twenty outputs in either a normal logic state (high or low
level) or a high impedance state. In the high impedance state, the outputs neither load nor drive the bus
lines significantly. The high impedance state and increased drive provide the capability to drive bus lines
without need for interface or pullup components. The output enable (OE) input does not affect the internal
operation of the flip flops. Old data can be retained or new data can be entered while the outputs are in the
high impedance state. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid
logic level.
Features
•
V
CC
= 2.3 V to 3.6 V
•
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25°C)
•
Typical V
OH
undershoot > 2.0 V (@V
CC
= 3.3 V, Ta = 25°C)
•
High output current
±24
mA (@V
CC
= 3.0 V)
•
Bus hold on data inputs eliminates the need for external pullup / pulldown resistors
HD74ALVCH16721
Function Table
Inputs
OE
L
L
L
L
H
CLKEN
H
L
L
L
X
CLK
X
↑
↑
L or H
X
D
X
H
L
X
X
Q
0 *1
H
L
Q
0 *1
Z
Output Q
H : High level
L : Low level
X : Immaterial
Z : High impedance
↑
: Low to high transition
Note: 1. Output level before the indicated steady state input conditions were established.
2
HD74ALVCH16721
Pin Arrangement
OE
1
Q1 2
Q2 3
GND 4
Q3 5
Q4 6
V
CC
7
Q5 8
Q6 9
Q7 10
GND 11
Q8 12
Q9 13
Q10 14
Q11 15
Q12 16
Q13 17
GND 18
Q14 19
Q15 20
Q16 21
V
CC
22
Q17 23
Q18 24
GND 25
Q19 26
Q20 27
NC 28
56 CLK
55 D1
54 D2
53 GND
52 D3
51 D4
50 V
CC
49 D5
48 D6
47 D7
46 GND
45 D8
44 D9
43 D10
42 D11
41 D12
40 D13
39 GND
38 D14
37 D15
36 D16
35 V
CC
34 D17
33 D18
32 GND
31 D19
30 D20
29
CLKEN
(Top view)
3
HD74ALVCH16721
Absolute Maximum Ratings
Item
Supply voltage
Input voltage
1
Output voltage
*1, 2
Input clamp current
Output clamp current
Continuous output current
V
CC
, GND current / pin
Maximum power dissipation
at Ta = 55°C (in still air)
*3
Storage temperature
Notes:
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
or I
GND
P
T
Tstg
Ratings
–0.5 to 4.6
–0.5 to 4.6
–0.5 to V
CC
+0.5
–50
±50
±50
±100
1
–65 to 150
Unit
V
V
V
mA
mA
mA
mA
W
°C
TSSOP
V
I
< 0
V
O
< 0 or V
O
> V
CC
V
O
= 0 to V
CC
Conditions
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage
to the device. These are stress ratings only, and functional operation of the device at these or
any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp
current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C
and a board trace length of 750 mils.
Recommended Operating Conditions
Item
Supply voltage
Input voltage
Output voltage
High level output current
Symbol
V
CC
V
I
V
O
I
OH
Min
2.3
0
0
—
—
—
Low level output current
I
OL
—
—
—
Input transition rise or fall rate
Operating temperature
∆t
/
∆v
Ta
0
–40
Max
3.6
V
CC
V
CC
–12
–12
–24
12
12
24
10
85
ns / V
°C
mA
Unit
V
V
V
mA
V
CC
= 2.3 V
V
CC
= 2.7 V
V
CC
= 3.0 V
V
CC
= 2.3 V
V
CC
= 2.7 V
V
CC
= 3.0 V
Conditions
Note: Unused control inputs must be held high or low to prevent them from floating.
4
HD74ALVCH16721
Logic Diagram
OE
CLK
CLKEN
D1
1
56
29
55
CE
C1
1D
2
Q1
To nineteen other channels
5
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