HD74AC138/HD74ACT138
1-of-8 Decoder/Demultiplexer
Description
The HD74AC138/HD74ACT138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally
suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow
parallel expansion to a 1-of-24 decoder using just three HD74AC138/HD74ACT138 devices or a 1-of-32
decoder using four HD74AC138/HD74ACT138 devices and one inverter.
Features
•
Demultiplexing Capability
•
Multiple Input Enable for Easy Expansion
•
Active LOW Mutually Exclusive Outputs
•
Outputs Source/Sink 24 mA
•
HD74ACT138 has TTL-Compatible Inputs
HD74AC138/HD74ACT138
Pin Arrangement
A
0
1
A
1
2
A
2
3
E
1
4
E
2
5
E
3
6
O
7
7
GND 8
(Top view)
16 V
CC
15
O
0
14
O
1
13
O
2
12
O
3
11
O
4
10
O
5
9
O
6
Logic Symbol
A
0
A
1
A
2
E
1
E
2
E
3
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
Pin Names
A
0
to A
2
E
1
to
E
2
E
3
O
0
to
O
7
Address Inputs
Enable Inputs
Enable Input
Outputs
2
HD74AC138/HD74ACT138
Functional Description
The HD74AC138/HD74ACT138 high-speed 1-of-8 decoder/demultiplexer accepts three binary weighted
inputs (A
0
, A
1
, A
2
) and, when enabled, provides eight mutually exclusive active-LOW outputs (O
0
to
O
7
).
The HD74AC138/HD74ACT138 features three Enable inputs, two active-Low (E
1
,
E
2
) and one active-High
(E
3
). All outputs will be High unless
E
1
and
E
2
are Low and E
3
is High. This multiple enabled function
allows easy parallel expansion of the device to a 1-of-32 (5 lines to 32 lines) decoder with just four
HD74AC138/HD74ACT138 devices and one inverter (See Figure a). The HD74AC138/HD74ACT138
can be used as an 8-output demultiplexer by using one of the active Low Enable inputs as the data input
and the other Enable inputs as strobes. The Enables inputs which are not used must be permanently tied to
their appropriate active-High or active-Low state.
Truth Table
Inputs
E
1
H
X
X
L
L
L
L
L
L
L
L
H :
L :
X :
E
2
X
H
X
L
L
L
L
L
L
L
L
E
3
X
X
L
H
H
H
H
H
H
H
H
A
0
X
X
X
L
H
L
H
L
H
L
H
A
1
X
X
X
L
L
H
H
L
L
H
H
A
2
X
X
X
L
L
L
L
H
H
H
H
Outputs
O
0
H
H
H
L
H
H
H
H
H
H
H
O
1
H
H
H
H
L
H
H
H
H
H
H
O
2
H
H
H
H
H
L
H
H
H
H
H
O
3
H
H
H
H
H
H
L
H
H
H
H
O
4
H
H
H
H
H
H
H
L
H
H
H
O
5
H
H
H
H
H
H
H
H
L
H
H
O
6
H
H
H
H
H
H
H
H
H
L
H
O
7
H
H
H
H
H
H
H
H
H
H
L
High Voltage Level
Low Voltage Level
Immaterial
3
HD74AC138/HD74ACT138
Logic Diagram
A
2
A
1
A
0
E
1
E
2
E
3
O
7
O
6
O
5
O
4
O
3
O
2
O
1
O
0
Please note that this diagram is provided only for the understanding of logic operations and should not be
used to estimate propagation delays.
Figure a: Expansion of 1-of-32 Decoding
A
0
A
1
A
2
’04
A
3
A
4
H
123
A
0
A
1
A
2
E
A
0
A
1
A
2
123
E
A
0
A
1
A
2
123
E
A
0
A
1
A
2
123
E
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
O
0
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
O
31
4
HD74AC138/HD74ACT138
DC Characteristics
(unless otherwise specified)
Item
Maximum quiescent supply current
Maximum quiescent supply current
Maximum I
CC
/input (HD74ACT138)
Symbol
I
CC
I
CC
I
CCT
Max
80
8.0
1.5
Unit
µA
µA
mA
Condition
V
IN
= V
CC
or ground, V
CC
= 5.5 V,
Ta = Worst case
V
IN
= V
CC
or ground, V
CC
= 5.5 V,
Ta = 25°C
V
IN
= V
CC
– 2.1 V, V
CC
= 5.5 V
Ta = Worst case
AC Characteristics: HD74AC138
Ta = +25°C
C
L
= 50 pF
Item
Propagation delay
A
n
to
O
n
Propagation delay
A
n
to
O
n
Propagation delay
E
1
or
E
2
to
O
n
Propagation delay
E
1
or
E
2
to
O
n
Propagation delay
E
3
to
O
n
Propagation delay
E
3
to
O
n
Note:
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
Symbol
t
PLH
V
CC
(V)*
1
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
1. Voltage Range 3.3 is 3.3 V
±
0.3 V
Voltage Range 5.0 is 5.0 V
±
0.5 V
Min
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Typ
8.5
6.5
8.0
6.0
11.0
8.0
9.5
7.0
11.0
8.0
8.5
6.0
Max
13.0
9.5
12.5
9.0
15.0
11.0
13.5
9.5
15.5
11.0
13.0
8.0
Ta = –40°C to +85°C
C
L
= 50 pF
Min
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max
15.0
10.5
14.0
10.5
16.0
12.0
15.0
10.5
16.5
12.5
14.0
9.5
ns
ns
ns
ns
ns
Unit
ns
5
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