HD74LV1GT125A
Bus Buffer Gate with 3–state Output /
CMOS Logic Level Shifter
REJ03D0123-0900
Rev.9.00
Mar 21, 2008
Description
The HD74LV1GT125A has a bus buffer gate with 3–state output in a 5 pin package. Output is disabled when the
associated output enable (OE) input is high. To ensure the high impedance state during power up or power down,
OE
should be connected to V
CC
through a pull-down resistor; the minimum value of the resistor is determined by the current
sourcing capability of the driver. The input protection circuitry on this device allows over voltage tolerance on the
input, allowing the device to be used as a logic–level translator from 3.0 V CMOS Logic to 5.0 V CMOS Logic or from
1.8 V CMOS logic to 3.0 V CMOS Logic while operating at the high-voltage power supply. Low voltage and high-
speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power
consumption extends the battery life.
Features
•
The basic gate function is lined up as Renesas uni logic series.
•
Supplied on emboss taping for high-speed automatic mounting.
•
TTL compatible input level.
Supply voltage range : 3.0 to 5.5 V
Operating temperature range : –40 to +85°C
•
Logic-level translate function
3.0 V CMOS logic
→
5.0 V CMOS logic (@V
CC
= 5.0 V)
1.8 V or 2.5 V CMOS logic
→
3.3 V CMOS logic (@V
CC
= 3.3 V)
•
All inputs V
IH
(Max.) = 5.5 V (@V
CC
= 0 V to 5.5 V)
All outputs V
O
(Max.) = 5.5 V (@V
CC
= 0 V, Output : Z)
•
Output current ±6 mA (@V
CC
= 3.0 V to 3.6 V), ±12 mA (@V
CC
= 4.5 V to 5.5 V)
•
All the logical input has hysteresis voltage for the slow transition.
•
Ordering Information
Part Name
HD74LV1GT125ACME
HD74LV1GT125AVSE
Note:
Package Type
CMPAK–5 pin
VSON–5 pin
Package Code
(Previous Code)
PTSP0005ZC-A
(CMPAK-5V)
PUSN0005KA-A
(TNP-5DV)
Package
Abbreviation
CM
VS
Taping Abbreviation
(Quantity)
E (3000 pcs/reel)
E (3000 pcs/reel)
Please consult the sales office for the above package availability.
REJ03D0123-0900 Rev.9.00, Mar 21, 2008
Page 1 of 7
HD74LV1GT125A
Outline and Article Indication
• HD74LV1GT125A
Index band
Marking
T
B
CMPAK–5
= Control code
• HD74LV1GT125A
Marking
T
B
VSON–5
= Control code
Function Table
Inputs
OE
L
L
H
H : High level
L : Low level
X : Immaterial
Z : High impedance
A
H
L
X
Output Y
H
L
Z
REJ03D0123-0900 Rev.9.00, Mar 21, 2008
Page 2 of 7
HD74LV1GT125A
Pin Arrangement
OE
1
5
V
CC
A
2
GND
3
4
Y
(Top view)
Absolute Maximum Ratings
Item
Supply voltage range
Input voltage range
*1
Output voltage range
*1, 2
Input clamp current
Output clamp current
Continuous output current
Continuous current through
V
CC
or GND
Maximum power dissipation
*3
at Ta = 25°C (in still air)
Storage temperature
Notes:
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
or I
GND
P
T
Tstg
Ratings
–0.5 to 7.0
–0.5 to 7.0
–0.5 to V
CC
+ 0.5
–0.5 to 7.0
–20
±50
±25
±50
200
–65 to 150
Unit
V
V
V
mA
mA
mA
mA
mW
°C
Output : H or L
V
CC
: OFF or Output : Z
V
I
< 0
V
O
< 0 or V
O
> V
CC
V
O
= 0 to V
CC
Test Conditions
The absolute maximum ratings are values, which must not individually be exceeded, and furthermore no two
of which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are
observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
Recommended Operating Conditions
Item
Supply voltage range
Input voltage range
Output voltage range
Symbol
V
CC
V
I
V
O
I
OH
Output current
I
OL
Input transition rise or fall rate
Operating free-air temperature
Note:
∆t
/
∆v
T
a
Min
3.0
0
0
0
—
—
—
—
0
0
–40
Max
5.5
5.5
V
CC
5.5
6
12
–6
–12
100
20
85
Unit
V
V
V
mA
mA
ns / V
°C
Conditions
Output : Z
V
CC
= 3.0 to 3.6 V
V
CC
= 4.5 to 5.5 V
V
CC
= 3.0 to 3.6 V
V
CC
= 4.5 to 5.5 V
V
CC
= 3.0 to 3.6 V
V
CC
= 4.5 to 5.5 V
Unused or floating inputs must be held high or low.
REJ03D0123-0900 Rev.9.00, Mar 21, 2008
Page 3 of 7
HD74LV1GT125A
Electrical Characteristic
•
Ta = –40 to 85°C
Item
Symbol
V
IH
Input voltage
V
IL
Hysteresis voltage
V
H
V
CC
(V) *
3.0 to 3.6
4.5 to 5.5
3.0 to 3.6
4.5 to 5.5
3.3
5.0
Min to Max
3.0
4.5
Min to Max
3.0
4.5
0 to 5.5
Min to Max
5.5
5.5
0
5.0
Min
1.5
2.0
—
—
—
—
V
CC
–0.1
2.48
3.8
—
—
—
—
—
—
—
—
—
Typ
—
—
—
—
0.10
0.15
—
—
—
—
—
—
—
—
—
—
—
3.0
Max
—
—
0.6
0.8
—
—
—
—
—
0.1
0.44
0.55
±1
±5
10
1.5
5
—
V
Unit
Test condition
V
V
V
T+
– V
T–
I
OH
= –50
µA
I
OH
= –6 mA
I
OH
= –12 mA
I
OL
= 50
µA
I
OL
= 6 mA
I
OL
= 12 mA
V
IN
= 5.5 V or GND
V
O
= 5.5 V or GND
V
IN
= V
CC
or GND,
I
O
= 0
One input V
IN
= 3.4 V,
other input V
CC
or GND
V
IN
or V
O
= 0 to 5.5 V
V
IN
= V
CC
or GND
V
OH
Output voltage
V
OL
Input current
Off state output
current
Quiescent
supply current
Output leakage current
Input capacitance
Note:
I
IN
I
OZ
I
CC
∆I
CC
I
OFF
C
IN
µA
µA
µA
mA
µA
pF
For conditions shown as Min or Max, use the appropriate values under recommended operating conditions.
Switching Characteristics
•
V
CC
= 3.3 ± 0.3 V
Item
Propagation
delay time
Enable time
Disable time
Symbol
t
PLH
t
PHL
t
ZH
t
ZL
t
HZ
t
LZ
Ta = 25°C
Min
Typ
Max
—
4.5
9.0
—
6.0
11.5
—
—
—
—
4.5
6.0
4.0
5.5
9.0
11.5
10.0
13.5
Ta = –40 to 85°C
Min
1.0
1.0
1.0
1.0
1.0
1.0
Max
10.5
13.0
10.5
13.0
11.5
15.0
Unit
ns
ns
ns
Test
Conditions
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
FROM
(Input)
A
OE
OE
TO
(Output)
Y
Y
Y
•
V
CC
= 5.0 ± 0.5 V
Item
Propagation
delay time
Enable time
Disable time
Symbol
t
PLH
t
PHL
t
ZH
t
ZL
t
HZ
t
LZ
Ta = 25°C
Min
Typ
Max
—
3.4
5.5
—
4.3
7.5
—
—
—
—
3.4
4.4
3.2
4.0
5.1
7.1
6.8
8.8
Ta = –40 to 85°C
Min
1.0
1.0
1.0
1.0
1.0
1.0
Max
6.5
8.5
6.0
8.0
8.0
10.0
Unit
ns
ns
ns
Test
Conditions
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
FROM
(Input)
A
OE
OE
TO
(Output)
Y
Y
Y
REJ03D0123-0900 Rev.9.00, Mar 21, 2008
Page 4 of 7
HD74LV1GT125A
Operating Characteristics
•
C
L
= 50 pF
Item
Power dissipation
capacitance
Symbol
C
PD
V
CC
(V)
5.0
Min
—
Ta = 25°C
Typ
11.5
Max
—
Unit
pF
Test Conditions
f = 10 MHz
Test Circuit
V
CC
V
CC
See Function Table
Input
Output
1 k
Ω
S1
C
L
=
15 or 50 pF
Pulse Generator
Z
OUT
= 50
Ω
OPEN
*1
See under table
GND
TEST
t
PLH
/ t
PHL
t
ZH
/ t
HZ
t
ZL
/ t
LZ
Note: 1. C
L
includes probe and jig capacitance.
S1
OPEN
GND
V
CC
REJ03D0123-0900 Rev.9.00, Mar 21, 2008
Page 5 of 7
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
