DATASHEET
BUFFER/CLOCK DRIVER
Description
The MK3807-01 is a low skew 3.3 V, 1 to 10 fanout buffer.
The large fanout from a single input line reduces loading on
the input clock. The TTL level outputs reduce noise levels on
the part. Typical applications are clock and signal
distribution.
MK3807-01
Features
•
•
•
•
Packaged in 20-pin SSOP
Pb (lead) free package
1 to 10 fanout buffer
Maximum skew between outputs of same package 0.35
ns
0.75 ns
•
Maximum skew between outputs of different packages
•
•
•
•
•
Max propagation delay of 3.8 ns
Operating voltage of 3.3 V
Advanced, low power, CMOS process
Industrial temperature range -40° C to +85° C
Hysteresis on all inputs
Block Diagram
CLK1
CLK2
CLK3
CLK4
IN
CLK5
CLK6
CLK7
CLK8
CLK9
CLK10
IDT™
BUFFER/CLOCK DRIVER
1
MK3807-01
REV G 051310
MK3807-01
BUFFER/CLOCK DRIVER
FAN OUT BUFFER
External Components
The MK3807-01 requires a minimum number of external
components for proper operation.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) The 0.01µF decoupling capacitors should be mounted on
the component side of the board as close to the VDD pins
as possible. No vias should be used between the
decoupling capacitors and VDD pins. The PCB trace to VDD
pin should be kept as short as possible, as should the PCB
trace to the ground via.
2) To minimize EMI, the 33Ω series termination resistor, (if
needed) should be placed close to the clock output.
Decoupling Capacitors
Decoupling capacitors of 0.01µF must be connected
between VDD and GND, as close to these pins as possible.
For optimum device performance, the decoupling capacitors
should be mounted on the component side of the PCB.
Avoid the use of vias in the decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock outputs and the
loads are over 1 inch, series termination should be used. To
series terminate a 50Ω trace (a commonly used trace
impedance) place a 33Ω resistor in series with the clock line,
as close to the clock output pin as possible. The nominal
impedance of the clock output is 20Ω
.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK3807-01. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
-40 to +85° C
-65 to +150° C
125° C
260° C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
-40
+3.135
Typ.
+3.3
Max.
+85
+3.465
Units
°
C
V
IDT™
BUFFER/CLOCK DRIVER
3
MK3807-01
REV G 051310
MK3807-01
BUFFER/CLOCK DRIVER
FAN OUT BUFFER
AC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V ±5%,
Ambient Temperature -40° C to +85° C
Parameter
Skew between outputs of same
package
Skew between opposite
transitions of same output
Propagation Delay IN to ON
Skew between outputs of
different package at same
power supply, temperature and
speed grade
Output Rise Time
0.8 V to 2.0 V
Output Fall Time
2.0 V to 0.8 V
Duty Cycle
Measured at VDD/2
Test Frequency
Symbol
tsk
9=(0)
tsk
(p)
tpLH/tpHL
tsk
(t)
Conditions
CL=50 pF,
RL=500Ω
CL=50 pF,
RL=500Ω
CL=50 pF,
RL=500Ω
CL=50 pF,
RL=500Ω
Min.
Typ.
Max. Units
0.35
0.35
ns
ns
ns
ns
1.5
3.8
0.75
tr
(o)
tf
(o)
DC
CL=50 pF,
RL=500Ω
CL=50 pF,
RL=500Ω
CL=50 pF,
RL=500Ω
45
1
1.5
1.5
55
100
ns
ns
%
MHz
IDT™
BUFFER/CLOCK DRIVER
5
MK3807-01
REV G 051310
单片机
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