FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20845-5E
FLASH MEMORY
CMOS
8M (1M
×
8/512K
×
16) BIT
MBM29LV800TA
-70/-90
/MBM29LV800BA
-70/-90
s
DESCRIPTION
The MBM29LV800TA/BA are a 8M-bit, 3.0 V-only Flash memory organized as 1M bytes of 8 bits each or 512K
words of 16 bits each. The MBM29LV800TA/BA are offered in a 48-pin TSOP(I), 44-pin SOP and 48-ball FBGA
,
packages. These devices are designed to be programmed in-system with the standard system 3.0 V V
CC
supply.
12.0 V V
PP
and 5.0 V V
CC
are not required for write or erase operations. The devices can also be reprogrammed
in standard EPROM programmers.
The standard MBM29LV800TA/BA offer access times 70 ns and 90 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE),
write enable (WE), and output enable (OE) controls.
The MBM29LV800TA/BA are pin and command set compatible with JEDEC standard E
2
PROMs. Commands are
written to the command register using standard microprocessor write timings. Register contents serve as input
to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch
addresses and data needed for the programming and erase operations. Reading data out of the devices is similar
to reading from 5.0 V and 12.0 V Flash or EPROM devices.
The MBM29LV800TA/BA are programmed by executing the program command sequence. This will invoke the
Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths
and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase
Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed
before executing the erase operation. During erase, the devices automatically time the erase pulse widths and
verify proper cell margin.
(Continued)
s
PRODUCT LINE UP
Part No.
V
CC
= 3.3 V
Ordering Part No.
V
CC
= 3.0 V
Max Address Access Time (ns)
Max CE Access Time (ns)
Max OE Access Time (ns)
+0.3 V
–0.3 V
+0.6 V
–0.3 V
MBM29LV800TA/MBM29LV800BA
-70
—
70
70
30
—
-90
90
90
35
MBM29LV800TA
-70/-90
/MBM29LV800BA
-70/-90
(Continued)
A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.)
The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29LV800TA/BA are erased when shipped from the
factory.
The devices feature single 3.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low V
CC
detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ
7
,
by the Toggle Bit feature on DQ
6
, or the RY/BY output pin. Once the end of a program or erase cycle has been
completed, the devices internally reset to the read mode.
Fujitsu’s Flash technology combines years of EPROM and E
2
PROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The MBM29LV800TA/BA memories electrically erase the entire chip
or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one
byte/word at a time using the EPROM programming mechanism of hot electron injection.
s
PACKAGES
48-pin Plastic TSOP (I)
Marking Side
Marking Side
48-pin Plastic TSOP (I)
44-pin Plastic SOP
Marking Side
(FPT-48P-M19)
48-pin Plastic FBGA
(FPT-48P-M20)
48-pin Plastic SCSP
(FPT-44P-M16)
(BGA-48P-M02)
(BGA-48P-M12)
(WLP-48P-M03)
2
MBM29LV800TA
-70/-90
/MBM29LV800BA
-70/-90
s
FEATURES
• Single 3.0 V Read, Program, and Erase
Minimizes system level power requirements
• Compatible with JEDEC-standard Commands
Uses same software commands as E
2
PROMs
• Compatible with JEDEC-standard Worldwide Pinouts
48-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)
44-pin SOP (Package suffix: PF)
48-ball FBGA (Package suffix: PBT)
48-ball SCSP (Package suffix: PW)
• Minimum 100,000 Program/Erase Cycles
• High performance
70 ns maximum access time
• Sector Erase Architecture
One 8K word, two 4K words, one 16K word, and fifteen 32K words sectors in word mode
One 16K byte, two 8K bytes, one 32K byte, and fifteen 64K bytes sectors in byte mode
Any combination of sectors can be concurrently erased. Also supports full chip erase
• Boot Code Sector Architecture
T = Top sector
B = Bottom sector
• Embedded Erase
TM
* Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded Program
TM
* Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit Feature for Detection of Program or Erase Cycle Completion
• Ready/Busy Output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic Sleep Mode
When addresses remain stable, automatically switch themselves to low power mode
• Low V
CC
Write Inhibit
≤
2.5 V
• Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
• Sector Protection
Hardware method disables any combination of sectors from program or erase operations
• Sector Protection Set Function by Extended Sector Protect Command
• Temporary Sector Unprotection
Temporary sector unprotection via the RESET pin
*: Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
3
MBM29LV800TA
-70/-90
/MBM29LV800BA
-70/-90
s
PIN ASSIGNMENTS
TSOP(I)
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
N.C.
N.C.
WE
RESET
N.C.
N.C.
RY/BY
A
18
A
17
A
7
A
6
A
5
A
4
A
3
A
2
A
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
(Marking Side)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A
16
BYTE
V
SS
DQ
15
/A
-1
DQ
7
DQ
14
DQ
6
DQ
13
DQ
5
DQ
12
DQ
4
V
CC
DQ
11
DQ
3
DQ
10
DQ
2
DQ
9
DQ
1
DQ
8
DQ
0
OE
V
SS
CE
A
0
RY/BY
A
18
A
17
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
CE
V
SS
OE
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
A
0
CE
V
SS
OE
DQ
0
DQ
8
DQ
1
DQ
9
DQ
2
DQ
10
DQ
3
DQ
11
V
CC
DQ
4
DQ
12
DQ
5
DQ
13
DQ
6
DQ
14
DQ
7
DQ
15
/A
-1
V
SS
BYTE
A
16
DQ
0
DQ
8
DQ
1
DQ
9
DQ
2
DQ
10
DQ
3
DQ
11
1
2
3
4
5
6
7
8
9
SOP
(Top View)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RESET
WE
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
BYTE
V
SS
DQ
15
/A
-1
DQ
7
DQ
14
DQ
6
DQ
13
DQ
5
DQ
12
DQ
4
V
CC
MBM29LV800TA/MBM29LV800BA
Normal Bend
10
11
12
13
14
15
16
17
18
19
20
21
22
(FPT-48P-M19)
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
17
A
18
RY/BY
N.C.
N.C.
RESET
WE
N.C.
N.C.
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
(Marking Side)
MBM29LV800TA/MBM29LV800BA
Reverse Bend
(FPT-44P-M16)
(FPT-48P-M20)
(Continued)
4
MBM29LV800TA
-70/-90
/MBM29LV800BA
-70/-90
(Continued)
(TOP VIEW)
Marking side
A1
B1
C1
D1
E1
F1
G1
H1
A2
B2
C2
D2
E2
F2
G2
H2
A3
B3
C3
D3
E3
F3
G3
H3
A4
B4
C4
D4
E4
F4
G4
H4
A5
B5
C5
D5
E5
F5
G5
H5
A6
B6
C6
D6
E6
F6
G6
H6
(BGA-48P-M02)
(BGA-48P-M12)
A1
B1
C1
D1
E1
F1
G1
H1
A
3
A
4
A
2
A
1
A
0
CE
OE
V
SS
A2
B2
C2
D2
E2
F2
G2
H2
A
7
A
17
A
6
A
5
DQ
0
DQ
8
DQ
9
DQ
1
A3
B3
C3
D3
E3
F3
G3
H3
RY/BY
N.C.
A
18
N.C.
DQ
2
DQ
10
DQ
11
DQ
3
A4
B4
C4
D4
E4
F4
G4
H4
WE
RESET
N.C.
N.C.
DQ
5
DQ
12
V
CC
DQ
4
A5
B5
C5
D5
E5
F5
G5
H5
A
9
A
8
A
10
A
11
DQ
7
DQ
14
DQ
13
DQ
6
A6
B6
C6
D6
E6
F6
G6
H6
A
13
A
12
A
14
A
15
A
16
BYTE
DQ
15
/A
-1
V
SS
SCSP
(Top View)
Marking side
A6
A
3
A5
A
7
A4
B6
A
4
B5
A
17
B4
C6
A
2
C5
A
6
C4
A
18
C3
D6
A
1
D5
A
5
D4
N.C
D3
N.C
D2
A
11
D1
A
15
E6
A
0
E5
DQ
0
E4
DQ
2
E3
F6
CE
F5
DQ
8
F4
G6
OE
G5
H6
V
SS
H5
DQ
9
DQ
1
G4
H4
RY/BY N.C
A3
B3
DQ
10
DQ
11
DQ
3
F3
G3
H3
DQ
4
H2
WE RESET N.C
A2
A
9
A1
A
13
B2
A
8
B1
A
12
C2
A
10
C1
A
14
DQ
5
DQ
12
V
CC
E2
F2
G2
DQ
7
DQ
14
DQ
13
DQ
6
E1
A
16
F1
G1
H1
BYTE DQ
15
/A
-1
V
SS
(WLP-48P-M03)
5
Microchip MCU
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