128Mb: x4, x8, x16
SDRAM
SYNCHRONOUS
DRAM
FEATURES
• PC100-, and PC133-compliant
• Fully synchronous; all signals registered on
positive edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO
PRECHARGE, and Auto Refresh Modes
• Self Refresh Mode; standard and low power
• 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
MT48LC32M4A2 – 8 Meg x 4 x 4 banks
MT48LC16M8A2 – 4 Meg x 8 x 4 banks
MT48LC8M16A2 – 2 Meg x 16 x 4 banks
For the latest data sheet, please refer to the Micron Web
site:
www.micron.com/dramds
PIN ASSIGNMENT (Top View)
54-Pin TSOP
x4 x8 x16
-
-
NC
DQ0
NC
DQ0
V
DD
DQ0
-
V
DD
Q
NC
DQ1
DQ1 DQ2
-
VssQ
NC
DQ3
DQ2 DQ4
-
V
DD
Q
NC
DQ5
DQ3 DQ6
-
VssQ
NC
DQ7
V
DD
-
NC DQML
-
WE#
-
CAS#
-
RAS#
CS#
-
BA0
-
BA1
-
A10
-
A0
-
A1
-
A2
-
A3
-
V
DD
-
x16 x8 x4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
-
-
NC
NC
-
NC
DQ1
-
NC
OPTIONS
MARKING
-
NC
• Configurations
32 Meg x 4 (8 Meg x 4 x 4 banks)
32M4
16 Meg x 8 (4 Meg x 8 x 4 banks)
16M8
8 Meg x 16 (2 Meg x 16 x 4 banks)
8M16
• WRITE Recovery (
t
WR)
t
WR = “2 CLK”
1
A2
• Package/Pinout
Plastic Package – OCPL
2
54-pin TSOP II (400 mil)
TG
54-pin TSOP II (400 mil) Lead-free
P
60-ball FBGA (8mm x 16mm)
FB
3
60-ball FBGA (8mm x 16mm)Lead-free BB
3
60-ball FBGA (11mm x 13mm)
FC
3
60-ball FBGA (11mm x 13mm) Lead-free BC
3
• Timing (Cycle Time)
10ns @ CL = 2 (PC100)
-8E
3,4,5
7.5ns @ CL = 3 (PC133)
-75
7.5ns @ CL = 2 (PC133)
-7E
6.0ns @ CL=3 (x16 only)
-6A
• Self Refresh
Standard
None
Low power
L
• Die Rev
:G
• Operating Temperature Range
Commercial (0
o
C to +70
o
C)
None
Industrial (-40
o
C to +85
o
C)
IT
3
NOTE:
1.
2.
3.
4.
5.
Refer to Micron Technical Note: TN-48-05.
Off-center parting line.
Consult Micron for availability.
Not recommended for new designs.
Shown for PC100 compatability.
-
-
-
-
-
-
-
-
-
-
-
-
-
Vss
DQ15 DQ7
VssQ
-
DQ14
NC
DQ13 DQ6
V
DD
Q
-
DQ12
NC
DQ11 DQ5
VssQ
-
DQ10
NC
DQ9 DQ4
V
DD
Q
-
DQ8
NC
-
Vss
-
NC
DQMH DQM
-
CLK
-
CKE
NC
-
A11
-
A9
-
A8
-
A7
-
A6
-
A5
-
A4
-
Vss
-
-
NC
-
NC
DQ3
-
NC
NC
-
NC
DQ2
-
NC
-
-
DQM
-
-
-
-
-
-
-
-
-
-
-
Note:
The # symbol indicates signal is active LOW. A dash (–)
indicates x8 and x4 pin function is same as x16 pin function.
32 Meg x 4
16 Meg x 8
8 Meg x 16
Configuration
8 Meg x 4 x 4 banks 4 Meg x 8 x 4 banks 2 Meg x 16 x 4 banks
Refresh Count
4K
4K
4K
Row Addressing
4K (A0–A11)
4K (A0–A11)
4K (A0–A11)
Bank Addressing
4 (BA0, BA1)
4 (BA0, BA1)
4 (BA0, BA1)
Column Addressing 2K (A0–A9, A11)
1K (A0–A9)
512 (A0–A8)
KEY TIMING PARAMETERS
SPEED
GRADE
-6A
-7E
-7E
-75
-8E
3,4,5
-75
-8E
3 ,4,5
CLOCK
ACCESS TIME SETUP
FREQUENCY CL = 2* CL = 3* TIME
167 MHz
143 MHz
133 MHz
133 MHz
125 MHz
100 MHz
100 MHz
–
–
5.4ns
–
–
6ns
6ns
5.4ns
5.4ns
–
5.4ns
6ns
–
–
1.5ns
1.5ns
1.5ns
1.5ns
2ns
1.5ns
2ns
HOLD
TIME
0.8ns
0.8ns
0.8ns
0.8ns
1ns
0.8ns
1ns
*CL = CAS (READ) latency
PDF: 09005aef8091e66d/Source: 09005aef8091e625
128MSDRAM.p65 – Rev. H; Pub. 12/04
1
©2001 Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
128Mb: x4, x8, x16
SDRAM
FBGA BALL ASSIGNMENT
(Top View)
32 Meg x 4
8 x 16mm and 11 x 13mm
1
2
3
4
5
6
7
8
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
NC
V
DD
Q
NC
NC
V
DD
Q
NC
NC
NC
NC
NC
A11
A8
A6
A4
Vss
VssQ
DQ3
NC
VssQ
DQ2
NC
Vss
DQM
CK
CKE
A9
A7
A5
Vss
V
DD
V
DD
Q
DQ0
NC
V
DD
Q
DQ1
NC
VDD
WE#
RAS#
NC
BA1
A0
A2
V
DD
NC
NC
VssQ
NC
NC
VssQ
NC
NC
CAS#
NC
CS#
BA0
A10
A1
A3
16 Meg x 8
8 x 16mm and 11 x 13mm
1
2
3
4
5
6
7
8
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
DQ7
NC
V
DD
Q
DQ5
NC
V
DD
Q
NC
NC
NC
NC
NC
A11
A8
A6
A4
Vss
VssQ
DQ6
NC
VssQ
DQ4
NC
Vss
DQM
CK
CKE
A9
A7
A5
Vss
V
DD
V
DD
Q
DQ1
NC
V
DD
Q
DQ3
NC
V
DD
WE#
RAS#
NC
BA1
A0
A2
V
DD
DQ0
NC
VssQ
DQ2
NC
VssQ
NC
NC
CAS#
NC
CS#
BA0
A10
A1
A3
Depopulated Balls
Depopulated Balls
PDF: 09005aef8091e66d/Source: 09005aef8091e625
128MSDRAM.p65 – Rev. H; Pub. 12/04
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc.
128Mb: x4, x8, x16
SDRAM
128Mb SDRAM PART NUMBERS
PART NUMBER
MT48LC32M4A2TG
MT48LC32M4A2P
MT48LC32M4A2FC*
MT48LC32M4A2BC*
MT48LC32M4A2FB*
MT48LC32M4A2BB*
MT48LC16M8A2TG
MT48LC16M8A2P
MT48LC16M8A2FC*
MT48LC16M8A2BC*
MT48LC16M8A2FB*
MT48LC16M8A2BB*
MT48LC8M16A2TG
MT48LC8M16A2P
*FBGA Device Decode
http://www.micron.com/support/FBGA/FBGA.asp
ARCHITECTURE
32 Meg x 4
32 Meg x 4
32 Meg x 4
32 Meg x 4
32 Meg x 4
32 Meg x 4
16 Meg x 8
16 Meg x 8
16 Meg x 8
16 Meg x 8
16 Meg x 8
16 Meg x 8
8 Meg x 16
8 Meg x 16
GENERAL DESCRIPTION
The Micron
®
128Mb SDRAM is a high-speed CMOS,
dynamic random-access memory containing 134,217,728
bits. It is internally configured as a quad-bank DRAM
with a synchronous interface (all signals are registered on
the positive edge of the clock signal, CLK). Each of the x4’s
33,554,432-bit banks is organized as 4,096 rows by 2,048
columns by 4 bits. Each of the x8’s 33,554,432-bit banks is
organized as 4,096 rows by 1,024 columns by 8 bits. Each
of the x16’s 33,554,432-bit banks is organized as 4,096
rows by 512 columns by 16 bits.
Read and write accesses to the SDRAM are burst ori-
ented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an AC-
TIVE command, which is then followed by a READ or
WRITE command. The address bits registered coinci-
dent with the ACTIVE command are used to select the
bank and row to be accessed (BA0, BA1 select the bank;
A0-A11 select the row). The address bits registered
coincident with the READ or WRITE command are used
to select the starting column location for the burst
access.
The SDRAM provides for programmable READ
or WRITE burst lengths of 1, 2, 4, or 8 locations, or the
full page, with a burst terminate option. An auto
precharge function may be enabled to provide a self-
timed row precharge that is initiated at the end of the
burst sequence.
The 128Mb SDRAM uses an internal pipelined
architecture to achieve high-speed operation. This
architecture is compatible with the 2n rule of prefetch
architectures, but it also allows the column address to be
changed on every clock cycle to achieve a high-speed,
fully random access. Precharging one bank while access-
ing one of the other three banks will hide the precharge
cycles and provide seamless high-speed, random-access
operation.
The 128Mb SDRAM is designed to operate in 3.3V
memory systems. An auto refresh mode is provided, along
with a power-saving, power-down mode. All inputs and
outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM operat-
ing performance, including the ability to synchronously
burst data at a high data rate with automatic column-
address generation, the ability to interleave between in-
ternal banks in order to hide precharge time and the
capability to randomly change column addresses on each
clock cycle during a burst access.
PDF: 09005aef8091e66d/Source: 09005aef8091e625
128MSDRAM.p65 – Rev. H; Pub. 12/04
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc.
128Mb: x4, x8, x16
SDRAM
TABLE OF CONTENTS
Functional Block Diagram – 32 Meg x 4 ..................
Functional Block Diagram – 16 Meg x 8 ..................
Functional Block Diagram – 8 Meg x 16 ..................
Pin Descriptions ...........................................................
Functional Description
.............................................
Initialization ...........................................................
Register Definition .................................................
mode register .....................................................
Burst Length ................................................
Burst Type ....................................................
CAS Latency .................................................
Operating Mode ..........................................
Write Burst Mode ........................................
Commands ...................................................................
Truth Table 1 (Commands and DQM Operation)
.............
Command Inhibit ..................................................
No Operation (NOP) ..............................................
Load mode register .................................................
Active .......................................................................
Read .......................................................................
Write .......................................................................
Precharge .................................................................
Auto Precharge .......................................................
Burst Terminate ......................................................
Auto Refresh ............................................................
Self Refresh ..............................................................
Operation ......................................................................
Bank/Row Activation .............................................
Reads .......................................................................
Writes .......................................................................
Precharge .................................................................
Power-Down ...........................................................
Clock Suspend ........................................................
Burst Read/Single Write ........................................
5
6
7
8
9
9
9
9
9
10
11
11
11
12
12
13
13
13
13
13
13
13
13
13
14
14
15
15
16
22
24
24
25
25
Concurrent Auto Precharge ..................................
Truth Table 2 (CKE)
.....................................................
Truth Table 3 (Current State, Same Bank)
.......................
Truth Table 4 (Current State, Different Bank)
..................
Absolute Maximum Ratings .......................................
DC Electrical Characteristics
and Operating Conditions .......................................
I
DD
Specifications and Conditions ............................
Capacitance ..................................................................
26
28
29
31
33
33
33
34
AC Electrical Characteristics and Recommended
Operating Conditions
(Timing Table) .............. 34
Timing Waveforms
Initialize and Load mode register ........................
Power-Down Mode ................................................
Clock Suspend Mode .............................................
Auto Refresh Mode ................................................
Self Refresh Mode ...................................................
Reads
Read – Without Auto Precharge .....................
Read – With Auto Precharge ...........................
Single Read – Without Auto Precharge .........
Single Read – With Auto Precharge ...............
Alternating Bank Read Accesses .....................
Read – Full-Page Burst ......................................
Read – DQM Operation ...................................
Writes
Write – Without Auto Precharge ...................
Write – With Auto Precharge .........................
Single Write – Without Auto Precharge ........
Single Write – With Auto Precharge ..............
Alternating Bank Write Accesses ...................
Write – Full-Page Burst ....................................
Write – DQM Operation ..................................
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
PDF: 09005aef8091e66d/Source: 09005aef8091e625
128MSDRAM.p65 – Rev. H; Pub. 12/04
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc.
128Mb: x4, x8, x16
SDRAM
FUNCTIONAL BLOCK DIAGRAM
32 Meg x 4 SDRAM
CKE
CLK
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
COMMAND
DECODE
MODE REGISTER
REFRESH 12
COUNTER
12
12
ROW-
ADDRESS
MUX
12
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
4096
BANK0
MEMORY
ARRAY
(4,096 x 2,048 x 4)
1
1
DQM
SENSE AMPLIFIERS
4
4096
DATA
OUTPUT
REGISTER
2
A0-A11,
BA0, BA1
14
ADDRESS
REGISTER
2
BANK
CONTROL
LOGIC
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
4
2048
(x4)
4
DQ0-
DQ3
DATA
INPUT
REGISTER
COLUMN
DECODER
COLUMN-
ADDRESS
COUNTER/
LATCH
11
11
PDF: 09005aef8091e66d/Source: 09005aef8091e625
128MSDRAM.p65 – Rev. H; Pub. 12/04
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc.
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