HB56U832 Series, HB56U432 Series
8,388,608-word
×
32-bit High Density Dynamic RAM Module
4,194,304-word
×
32-bit High Density Dynamic RAM Module
ADE-203-736A (Z)
Rev.1.0
Feb. 7, 1997
Description
The HB56U832 is a 8M
×
32 dynamic RAM module, mounted 16 pieces of 16-Mbit DRAM (HM5117405)
sealed in SOJ package. The HB56U432 is a 4M
×
32 dynamic RAM module, mounted 8 pieces of 16-Mbit
DRAM (HM5117405) sealed in SOJ package. The HB56U832, HB56U432 offer Extended Data Out
(EDO) Page Mode as a high speed access time. An outline of the HB56U832, HB56U432 is 72-pin single
in-line package. Therefore, the HB56U832, HB56U432 make high density mounting possible without
surface mount technology. The HB56U832, HB56U432 provide common data inputs and outputs.
Decoupling capacitors are mounted on the module board.
Features
•
72-pin single in-line package
Outline: 107.95 mm (Length)
×
25.40 mm (Height)
×
9.14/5.28 mm (Thickness)
Lead pitch: 1.27 mm
Single 5 V (±5%) supply
High speed
Access time: t
RAC
= 50/60/70 ns (max)
Low power dissipation
Active mode: 4.41/3.99/3.57W (max) (HB56U832 Series)
4.20/3.78/3.36 W (max) (HB56U432 Series)
Standby mode (TTL): 168 mW (max) (HB56U832 Series)
(TTL): 84 mW (max) (HB56U432 Series)
(CMOS): 12.6 mW (max) (L-version) (HB56U832 Series)
(CMOS): 6.3 mW (max) (L-version) (HB56U432 Series)
EDO page mode capability
Refresh period
2048 refresh cycles: 32 ms
128 ms (L-version)
•
•
•
•
•
HB56U832 Series, HB56U432 Series
Pin Description
Pin name
A0 to A10
Function
Address inputs:
Row address:
Column address:
Refresh address:
DQ0 to DQ31
CAS0
to
CAS3
RAS0
to
RAS3
WE
V
CC
V
SS
PD1 to PD4
NC
Data-in/Data-out
Column address strobe
Row address strobe
Read/Write enable
Power supply
Ground
Presence detect pin
No connection
A0 to A10
A0 to A10
A0 to A10
Presence Detect Pin Arrangement
(HB56U832)
Function
Pin No.
67
68
69
70
Pin name
PD1
PD2
PD3
PD4
50 ns
NC
V
SS
V
SS
V
SS
60 ns
NC
V
SS
NC
NC
70 ns
NC
V
SS
V
SS
NC
Presence Detect Pin Arrangement
(HB56U432)
Function
Pin No.
67
68
69
70
Pin name
PD1
PD2
PD3
PD4
50 ns
V
SS
NC
V
SS
V
SS
60 ns
V
SS
NC
NC
NC
70 ns
V
SS
NC
V
SS
NC
4
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
